| /external/libvpx/vpx_dsp/arm/ |
| D | fdct_neon.h | 49 int32x4_t *sub_hi) { in butterfly_one_coeff_s16_s32_fast() argument
58 *sub_hi = vqrdmulhq_s32(vsubl_s16(a_hi, b_hi), c); in butterfly_one_coeff_s16_s32_fast()
68 int32x4_t add_lo, add_hi, sub_lo, sub_hi; in butterfly_one_coeff_s16_s32_fast_narrow() local
70 &sub_hi); in butterfly_one_coeff_s16_s32_fast_narrow()
72 *sub = vcombine_s16(vmovn_s32(sub_lo), vmovn_s32(sub_hi)); in butterfly_one_coeff_s16_s32_fast_narrow()
106 int32x4_t *sub_hi) { in butterfly_one_coeff_s16_s32() argument
116 *sub_hi = vrshrq_n_s32(diff1, DCT_CONST_BITS); in butterfly_one_coeff_s16_s32()
140 int32x4_t *add_hi, int32x4_t *sub_lo, int32x4_t *sub_hi) { in butterfly_one_coeff_s32_noround() argument
148 *sub_hi = vmlsq_n_s32(a4, b_hi, constant); in butterfly_one_coeff_s32_noround()
172 int32x4_t *add_hi, int32x4_t *sub_lo, int32x4_t *sub_hi) { in butterfly_one_coeff_s32_fast() argument
[all …]
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| /external/swiftshader/third_party/llvm-10.0/configs/common/lib/Target/Mips/ |
| D | MipsGenRegisterInfo.inc | 557 sub_hi, // 8
699 { 32, 32 }, // sub_hi
3935 …4", "sub_dsp16_19", "sub_dsp20", "sub_dsp21", "sub_dsp22", "sub_dsp23", "sub_hi", "sub_lo", "sub_h…
3947 LaneBitmask(0x00000040), // sub_hi
4058 0x00000000, 0x00000100, 0x00000000, // sub_hi
4064 0x00000000, 0x00000100, 0x00000000, // sub_hi
4143 0x00000000, 0x02010000, 0x00000000, // sub_hi
4200 0x00000000, 0x02000000, 0x00000000, // sub_hi
4316 0x00000000, 0x00000000, 0x00000020, // sub_hi
6161 { Mips::sub_hi_then_sub_32, 0, 0, 0, 0, 0, 0, Mips::sub_hi, Mips::sub_lo, 0, 0, },
[all …]
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| /external/libvpx/vp9/common/arm/neon/ |
| D | vp9_highbd_iht16x16_add_neon.c | 136 const int64x2x2_t sub_hi = vsubq_s64_dual(in0[1], in1[1]); in highbd_sub_dct_const_round_shift_low_8() local
141 out_hi.val[0] = vrshrn_n_s64(sub_hi.val[0], DCT_CONST_BITS); in highbd_sub_dct_const_round_shift_low_8()
142 out_hi.val[1] = vrshrn_n_s64(sub_hi.val[1], DCT_CONST_BITS); in highbd_sub_dct_const_round_shift_low_8()
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| D | vp9_highbd_iht8x8_add_neon.c | 82 const int64x2_t sub_hi = vsubq_s64(in0[1], in1[1]); in highbd_sub_dct_const_round_shift_low_8() local
84 const int32x2_t out_hi = vrshrn_n_s64(sub_hi, DCT_CONST_BITS); in highbd_sub_dct_const_round_shift_low_8()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AVR/ |
| D | AVRAsmPrinter.cpp | 121 Reg = TRI.getSubReg(Reg, ByteNumber % BytesPerReg ? AVR::sub_hi in PrintAsmOperand()
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| D | AVRRegisterInfo.td | 32 def sub_hi : SubRegIndex<8, 8>;
79 let SubRegIndices = [sub_lo, sub_hi],
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| D | AVRRegisterInfo.cpp | 273 HiReg = getSubReg(Reg, AVR::sub_hi); in splitReg()
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| D | AVRFrameLowering.cpp | 334 .addReg(TRI.getSubReg(SrcReg, AVR::sub_hi), in fixStackStores()
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| D | AVRInstrInfo.td | 2097 (EXTRACT_SUBREG DREGS:$src, sub_hi)>;
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| /external/llvm/lib/Target/AVR/ |
| D | AVRRegisterInfo.td | 33 def sub_hi : SubRegIndex<8, 8>;
80 let SubRegIndices = [sub_lo, sub_hi],
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| D | AVRInstrInfo.td | 1975 (EXTRACT_SUBREG DREGS:$src, sub_hi)>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 575 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi()
617 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; in expandExtractElementF64()
628 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) { in expandExtractElementF64()
700 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) in expandBuildPairF64()
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| D | MipsRegisterInfo.td | 17 def sub_hi : SubRegIndex<32, 32>;
56 let SubRegIndices = [sub_lo, sub_hi];
62 let SubRegIndices = [sub_lo, sub_hi];
75 let SubRegIndices = [sub_lo, sub_hi];
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| D | MipsSEFrameLowering.cpp | 192 unsigned Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
249 unsigned DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC()
441 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); in emitPrologue()
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| /external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| D | MipsRegisterInfo.td | 16 def sub_hi : SubRegIndex<32, 32>;
55 let SubRegIndices = [sub_lo, sub_hi];
61 let SubRegIndices = [sub_lo, sub_hi];
74 let SubRegIndices = [sub_lo, sub_hi];
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| D | MipsSEInstrInfo.cpp | 734 Register DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); in expandPseudoMTLoHi()
777 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; in expandExtractElementF64()
788 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) { in expandExtractElementF64()
866 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) in expandBuildPairF64()
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| D | MipsSEFrameLowering.cpp | 211 Register Hi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandLoadACC()
269 Register DstHi = RegInfo.getSubReg(Dst, Mips::sub_hi); in expandCopyACC()
466 MRI->getDwarfRegNum(RegInfo.getSubReg(Reg, Mips::sub_hi), true); in emitPrologue()
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