| /art/disassembler/ |
| D | disassembler_riscv64.cc | 219 /*out*/ const char** rs2);
448 uint32_t rs2 = GetRs2(insn32); in Print32BCond() local
449 if (rs2 == Zero) { in Print32BCond()
454 os_ << (funct3 == 4u ? "bgtz " : "blez ") << XRegName(rs2); in Print32BCond()
456 os_ << opcode << " " << XRegName(rs1) << ", " << XRegName(rs2); in Print32BCond()
507 /*out*/ const char** rs2) { in DecodeRVVMemMnemonic() argument
595 *rs2 = VRegName(GetRs2(insn32)); in DecodeRVVMemMnemonic()
609 *rs2 = XRegName(GetRs2(insn32)); in DecodeRVVMemMnemonic()
623 *rs2 = VRegName(GetRs2(insn32)); in DecodeRVVMemMnemonic()
637 const char* rs2 = nullptr; in Print32FLoad() local
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| /art/compiler/utils/riscv64/ |
| D | assembler_riscv64.h | 266 void Beq(XRegister rs1, XRegister rs2, int32_t offset);
267 void Bne(XRegister rs1, XRegister rs2, int32_t offset);
268 void Blt(XRegister rs1, XRegister rs2, int32_t offset);
269 void Bge(XRegister rs1, XRegister rs2, int32_t offset);
270 void Bltu(XRegister rs1, XRegister rs2, int32_t offset);
271 void Bgeu(XRegister rs1, XRegister rs2, int32_t offset);
283 void Sb(XRegister rs2, XRegister rs1, int32_t offset);
284 void Sh(XRegister rs2, XRegister rs1, int32_t offset);
285 void Sw(XRegister rs2, XRegister rs1, int32_t offset);
286 void Sd(XRegister rs2, XRegister rs1, int32_t offset);
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| D | assembler_riscv64.cc | 116 void Riscv64Assembler::Beq(XRegister rs1, XRegister rs2, int32_t offset) { in Beq() argument
118 if (rs2 == Zero && IsShortReg(rs1) && IsInt<9>(offset)) { in Beq()
121 } else if (rs1 == Zero && IsShortReg(rs2) && IsInt<9>(offset)) { in Beq()
122 CBeqz(rs2, offset); in Beq()
127 EmitB(offset, rs2, rs1, 0x0, 0x63); in Beq()
130 void Riscv64Assembler::Bne(XRegister rs1, XRegister rs2, int32_t offset) { in Bne() argument
132 if (rs2 == Zero && IsShortReg(rs1) && IsInt<9>(offset)) { in Bne()
135 } else if (rs1 == Zero && IsShortReg(rs2) && IsInt<9>(offset)) { in Bne()
136 CBnez(rs2, offset); in Bne()
141 EmitB(offset, rs2, rs1, 0x1, 0x63); in Bne()
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| /art/compiler/optimizing/ |
| D | code_generator_riscv64.h | 288 void FAdd(FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type);
303 void ShNAdd(XRegister rd, XRegister rs1, XRegister rs2, DataType::Type type);
394 void FpBinOp(Reg rd, FRegister rs1, FRegister rs2, DataType::Type type);
395 void FSub(FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type);
396 void FDiv(FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type);
397 void FMul(FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type);
398 void FMin(FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type);
399 void FMax(FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type);
400 void FEq(XRegister rd, FRegister rs1, FRegister rs2, DataType::Type type);
401 void FLt(XRegister rd, FRegister rs1, FRegister rs2, DataType::Type type);
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| D | code_generator_riscv64.cc | 797 Reg rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FpBinOp() argument
800 (assembler->*opS)(rd, rs1, rs2); in FpBinOp()
803 (assembler->*opD)(rd, rs1, rs2); in FpBinOp()
808 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FAdd() argument
809 FpBinOp<FRegister, &Riscv64Assembler::FAddS, &Riscv64Assembler::FAddD>(rd, rs1, rs2, type); in FAdd()
813 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FSub() argument
814 FpBinOp<FRegister, &Riscv64Assembler::FSubS, &Riscv64Assembler::FSubD>(rd, rs1, rs2, type); in FSub()
818 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FDiv() argument
819 FpBinOp<FRegister, &Riscv64Assembler::FDivS, &Riscv64Assembler::FDivD>(rd, rs1, rs2, type); in FDiv()
823 FRegister rd, FRegister rs1, FRegister rs2, DataType::Type type) { in FMul() argument
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| D | intrinsics_riscv64.cc | 313 EmitMemoryPoke(invoke, [&](XRegister rs2, XRegister rs1) { __ Sb(rs2, rs1, 0); }); in VisitMemoryPokeByte() argument
322 EmitMemoryPoke(invoke, [&](XRegister rs2, XRegister rs1) { __ Sw(rs2, rs1, 0); }); in VisitMemoryPokeIntNative() argument
331 EmitMemoryPoke(invoke, [&](XRegister rs2, XRegister rs1) { __ Sd(rs2, rs1, 0); }); in VisitMemoryPokeLongNative() argument
340 EmitMemoryPoke(invoke, [&](XRegister rs2, XRegister rs1) { __ Sh(rs2, rs1, 0); }); in VisitMemoryPokeShortNative() argument
1480 Location rs2, in EmitBlt32() argument
1483 if (rs2.IsConstant()) { in EmitBlt32()
1484 __ Li(temp, rs2.GetConstant()->AsIntConstant()->GetValue()); in EmitBlt32()
1487 __ Blt(rs1, rs2.AsRegister<XRegister>(), label); in EmitBlt32()
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