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/external/llvm/test/CodeGen/AArch64/
D	arm64-neon-mul-div.ll	`1 ; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon \| FileCheck %s 5 ; CHECK-LABEL: mul8xi8: 6 ; CHECK: mul {{v[0-9]+}}.8b, {{v[0-9]+}}.8b, {{v[0-9]+}}.8b 12 ; CHECK-LABEL: mul16xi8: 13 ; CHECK: mul {{v[0-9]+}}.16b, {{v[0-9]+}}.16b, {{v[0-9]+}}.16b 19 ; CHECK-LABEL: mul4xi16: 20 ; CHECK: mul {{v[0-9]+}}.4h, {{v[0-9]+}}.4h, {{v[0-9]+}}.4h 26 ; CHECK-LABEL: mul8xi16: 27 ; CHECK: mul {{v[0-9]+}}.8h, {{v[0-9]+}}.8h, {{v[0-9]+}}.8h 33 ; CHECK-LABEL: mul2xi32: [all …]`
D	fp-dp3.ll	1 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=aarch64-none-linux-gnu -fp-contract=fast \| FileCh… 2 ; RUN: llc -verify-machineinstrs -o - %s -mtriple=arm64-apple-ios7.0 \| FileCheck %s -check-prefix=C… 8 ; CHECK-LABEL: test_fmadd: 9 ; CHECK-NOFAST-LABEL: test_fmadd: 11 ; CHECK: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} 12 ; CHECK-NOFAST: fmadd {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} 17 ; CHECK-LABEL: test_fmsub: 18 ; CHECK-NOFAST-LABEL: test_fmsub: 19 %nega = fsub float -0.0, %a 21 ; CHECK: fmsub {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}} [all …]
D	logical_shifted_reg.ll	`1 ; RUN: llc -verify-machineinstrs < %s -mtriple=aarch64-none-linux-gnu \| FileCheck %s 3 @var1_32 = global i32 0 4 @var2_32 = global i32 0 6 @var1_64 = global i64 0 7 @var2_64 = global i64 0 10 ; CHECK-LABEL: logical_32bit: 15 %neg_val2 = xor i32 -1, %val2 18 ; CHECK: and {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} 21 ; CHECK: bic {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} 25 ; CHECK: orr {{w[0-9]+}}, {{w[0-9]+}}, {{w[0-9]+}} [all …]`
/external/llvm/test/CodeGen/PowerPC/
D	vec_cmpd.ll	3 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s \| FileCheck %s 4 ; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s \| FileCheck %s 10 ; CHECK-LABEL: v2si64_cmp: 18 ; CHECK-LABEL: v4si64_cmp 19 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 20 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 27 ; CHECK-LABEL: v8si64_cmp 28 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 29 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} 30 ; CHECK: vcmpequd {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}} [all …]
/external/llvm/test/CodeGen/AMDGPU/
D	global_atomics_i64.ll	1 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN -ch… 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN -chec… 4 ; GCN-LABEL: {{^}}atomic_add_i64_offset: 5 ; GCN: buffer_atomic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32{{$}} 13 ; GCN-LABEL: {{^}}atomic_add_i64_ret_offset: 14 ; GCN: buffer_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:32 … 24 ; GCN-LABEL: {{^}}atomic_add_i64_addr64_offset: 25 ; CI: buffer_atomic_add_x2 v{{\[[0-9]+:[0-9]+\]}}, v[{{[0-9]+}}:{{[0-9]+}}], s[{{[0-9]+}}:{{[0-9]+}… 26 ; VI: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}} 35 ; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64_offset: [all …]
D	flat_atomics_i64.ll	1 ; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN %s 4 ; GCN-LABEL: {{^}}atomic_add_i64_offset: 5 ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}} 13 ; GCN-LABEL: {{^}}atomic_add_i64_ret_offset: 14 ; GCN: flat_atomic_add_x2 [[RET:v\[[0-9]+:[0-9]+\]]], v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}} … 15 ; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RET]] 24 ; GCN-LABEL: {{^}}atomic_add_i64_addr64_offset: 25 ; GCN: flat_atomic_add_x2 v[{{[0-9]+:[0-9]+}}], v{{\[[0-9]+:[0-9]+\]}}{{$}} 34 ; GCN-LABEL: {{^}}atomic_add_i64_ret_addr64_offset: [all …]
D	global_atomics.ll	1 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN -check-prefix=SI … 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN -chec… 4 ; FUNC-LABEL: {{^}}atomic_add_i32_offset: 5 ; GCN: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], 0 offset:16{{$}} 13 ; FUNC-LABEL: {{^}}atomic_add_i32_soffset: 14 ; GCN: s_mov_b32 [[SREG:s[0-9]+]], 0x8ca0 15 ; GCN: buffer_atomic_add v{{[0-9]+}}, off, s[{{[0-9]+}}:{{[0-9]+}}], [[SREG]]{{$}} 23 ; FUNC-LABEL: {{^}}atomic_add_i32_huge_offset: 24 ; SI-DAG: v_mov_b32_e32 v[[PTRLO:[0-9]+]], 0xdeac 25 ; SI-DAG: v_mov_b32_e32 v[[PTRHI:[0-9]+]], 0xabcd [all …]
D	private-element-size.ll	1 …-march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-16 -… 2 …-march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-8 -v… 3 …-march=amdgcn -mtriple=amdgcn-unknown-amdhsa -mattr=-promote-alloca,+max-private-element-size-4 -v… 6 ; ALL-LABEL: {{^}}private_elt_size_v4i32: 8 ; HSA-ELT16: private_element_size = 3 9 ; HSA-ELT8: private_element_size = 2 10 ; HSA-ELT4: private_element_size = 1 13 ; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} 14 ; HSA-ELT16-DAG: buffer_store_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen offset:… 15 ; HSA-ELT16-DAG: buffer_load_dwordx4 {{v\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}}, s[0:3], s9 offen{{$}} [all …]
D	fsub64.ll	1 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s \| FileCheck -check-prefix=SI %s 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s \| FileCheck -check-prefix=SI %s 4 declare double @llvm.fabs.f64(double) #0 6 ; SI-LABEL: {{^}}fsub_f64: 7 ; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -v\[[0-9]+:[0-9]+\]}} 17 ; SI-LABEL: {{^}}fsub_fabs_f64: 18 ; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], -\\|v\[[0-9]+:[0-9]+\]\\|}} 23 %r1.fabs = call double @llvm.fabs.f64(double %r1) #0 29 ; SI-LABEL: {{^}}fsub_fabs_inv_f64: 30 ; SI: v_add_f64 {{v\[[0-9]+:[0-9]+\], \|v\[[0-9]+:[0-9]+\]\|, -v\[[0-9]+:[0-9]+\]}} [all …]
D	mad-combine.ll	1 ; Make sure we still form mad even when unsafe math or fp-contract is allowed instead of fma. 3 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s \| FileCheck -check-prefix=SI -chec… 4 ; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s \| FileCheck -che… 5 …RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -enable-unsafe-fp-math < %s \| FileCheck … 8 …-march=amdgcn -mcpu=tahiti -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s \| F… 9 …-march=amdgcn -mcpu=verde -mattr=+fp32-denormals -fp-contract=fast -verify-machineinstrs < %s \| Fi… 11 declare i32 @llvm.amdgcn.workitem.id.x() #0 12 declare float @llvm.fabs.f32(float) #0 13 declare float @llvm.fma.f32(float, float, float) #0 14 declare float @llvm.fmuladd.f32(float, float, float) #0 [all …]
D	srl.ll	1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s \| FileCheck -check-prefix=SI -check… 2 ; XUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s \| FileCheck -check-prefix=VI -check… 3 ; RUN: llc -march=r600 -mcpu=redwood < %s \| FileCheck -check-prefix=EG -check-prefix=FUNC %s 5 declare i32 @llvm.r600.read.tidig.x() #0 7 ; FUNC-LABEL: {{^}}lshr_i32: 8 ; SI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 9 ; VI: v_lshrrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 10 ; EG: LSHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 20 ; FUNC-LABEL: {{^}}lshr_v2i32: 21 ; SI: v_lshr_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} [all …]
D	sra.ll	1 ; RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN -chec… 2 ; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s \| FileCheck -check-prefix=GCN -chec… 3 ; RUN: llc -march=r600 -mcpu=redwood < %s \| FileCheck -check-prefix=EG -check-prefix=FUNC %s 5 declare i32 @llvm.r600.read.tidig.x() #0 7 ; FUNC-LABEL: {{^}}ashr_v2i32: 8 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 9 ; SI: v_ashr_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 11 ; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 12 ; VI: v_ashrrev_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 14 ; EG: ASHR {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} [all …]
D	fma-combine.ll	1 …RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs -fp-contract=fast < %s \| FileCheck -chec… 2 … RUN: llc -march=amdgcn -mcpu=verde -verify-machineinstrs -fp-contract=fast < %s \| FileCheck -chec… 4 declare i32 @llvm.amdgcn.workitem.id.x() #0 5 declare double @llvm.fabs.f64(double) #0 6 declare double @llvm.fma.f64(double, double, double) #0 7 declare float @llvm.fma.f32(float, float, float) #0 9 ; (fadd (fmul x, y), z) -> (fma x, y, z) 10 ; FUNC-LABEL: {{^}}combine_to_fma_f64_0: 11 ; SI-DAG: buffer_load_dwordx2 [[A:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\… 12 ; SI-DAG: buffer_load_dwordx2 [[B:v\[[0-9]+:[0-9]+\]]], v{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\… [all …]
D	shl.ll	1 ; RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs \| FileCheck -check-prefix=GCN -chec… 2 ; XUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs \| FileCheck -check-prefix=GCN -chec… 3 ; RUN: llc < %s -march=r600 -mcpu=redwood \| FileCheck --check-prefix=EG %s 5 declare i32 @llvm.r600.read.tidig.x() #0 9 ;EG: LSHL {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 10 ;EG: LSHL {{\? }}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} 13 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 14 ;SI: v_lshl_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 17 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} 18 ;VI: v_lshlrev_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} [all …]
D	insert_vector_elt.ll	1 ; RUN: llc -verify-machineinstrs -march=amdgcn -mattr=+max-private-element-size-16 < %s \| FileCheck… 2 ; RUN: llc -verify-machineinstrs -march=amdgcn -mcpu=tonga -mattr=+max-private-element-size-16 < %s… 6 ; individual elements instead of 128-bit stores. 12 ; GCN-LABEL: {{^}}insertelement_v4f32_0: 14 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 15 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 16 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 17 ; GCN-DAG: v_mov_b32_e32 v{{[0-9]+}}, s{{[0-9]+}} 18 ; GCN-DAG: v_mov_b32_e32 [[CONSTREG:v[0-9]+]], 0x40a00000 19 ; GCN-DAG: v_mov_b32_e32 v[[LOW_REG:[0-9]+]], [[CONSTREG]] [all …]
/external/conscrypt/repackaged/common/src/main/java/com/android/org/conscrypt/
D	AddressUtils.java	9 * http://www.apache.org/licenses/LICENSE-2.0 29 private static final String IP_PATTERN = "^(?:(?:(?:25[0-5]\|2[0-4][0-9]\|[01]?[0-9]?[0-9])\\.){" 30 + "3}(?:25[0-5]\|2[0-4][0-9]\|[01]?[0-9]?[0-9]))\|" 31 + "(?i:(?:(?:[0-9a-f]{1,4}:){7}(?:[0-9a-f]{1,4}\|:))\|(?:(?:[0-9a-f]{1,4}:){6}(?::[0-9a-" 32 + "f]{1,4}\|(?:(?:25[0-5]\|2[0-4][0-9]\|1[0-9][0-9]\|[1-9]?[0-9])(?:\\.(?:25[0-5]\|2[0-4][" 33 + "0-9]\|1[0-9][0-9]\|[1-9]?[0-9])){3})\|:))\|(?:(?:[0-9a-f]{1,4}:){5}(?:(?:(?::[0-9a-f]{" 34 + "1,4}){1,2})\|:(?:(?:25[0-5]\|2[0-4][0-9]\|1[0-9][0-9]\|[1-9]?[0-9])(?:\\.(?:25[0-5]\|2[" 35 + "0-4][0-9]\|1[0-9][0-9]\|[1-9]?[0-9])){3})\|:))\|(?:(?:[0-9a-f]{1,4}:){4}(?:(?:(?::[0-" 36 + "9a-f]{1,4}){1,3})\|(?:(?::[0-9a-f]{1,4})?:(?:(?:25[0-5]\|2[0-4][0-9]\|1[0-9][0-9]\|[1-" 37 + "9]?[0-9])(?:\\.(?:25[0-5]\|2[0-4][0-9]\|1[0-9][0-9]\|[1-9]?[0-9])){3}))\|:))\|(?:(?:[0-" [all …]
/external/conscrypt/common/src/main/java/org/conscrypt/
D	AddressUtils.java	`8 * http://www.apache.org/licenses/LICENSE-2.0 28 …al String IP_PATTERN = "^(?:(?:(?:25[0-5]\|2[0-4][0-9]\|[01]?[0-9]?[0-9])\\.){3}(?:25[0-5]\|2[0-4][0-… 29 …0-9a-f]{1,4}:){7}(?:[0-9a-f]{1,4}\|:))\|(?:(?:[0-9a-f]{1,4}:){6}(?::[0-9a-f]{1,4}\|(?:(?:25[0-5]\|2[0-… 45 \|\| sniHostname.indexOf('.') != -1) in isValidSniHostname() 48 && sniHostname.indexOf('\0') == -1; in isValidSniHostname() 55 /* This is here for backwards compatibility for pre-Honeycomb devices. */ in isLiteralIpAddress()`
/external/python/dateutil/dateutil/test/
D	test_rrule.py	`1 # -- coding: utf-8 -- 40 dtstart=datetime(1997, 9, 2, 9, 0))), 52 dtstart=datetime(1997, 9, 2, 9, 0))), 53 [datetime(1997, 9, 2, 9, 0), 54 datetime(1998, 9, 2, 9, 0), 55 datetime(1999, 9, 2, 9, 0)]) 61 dtstart=datetime(1997, 9, 2, 9, 0))), 62 [datetime(1997, 9, 2, 9, 0), 63 datetime(1999, 9, 2, 9, 0), 64 datetime(2001, 9, 2, 9, 0)]) [all …]`
/external/python/dateutil/docs/
D	rrule.rst	`6 :undoc-members: 9 ------- 15 --------- 21 -------------- 52 [datetime.datetime(1997, 9, 2, 9, 0), 53 datetime.datetime(1997, 9, 3, 9, 0), 54 datetime.datetime(1997, 9, 4, 9, 0), 55 datetime.datetime(1997, 9, 5, 9, 0), 56 datetime.datetime(1997, 9, 6, 9, 0), 57 datetime.datetime(1997, 9, 7, 9, 0), [all …]`
/external/cronet/tot/third_party/icu/source/test/testdata/
D	regextst.txt	`3 # Copyright (c) 2001-2015 International Business Machines 17 # if any, is group 0, as in <0>matched text</0> 24 # s dot-matches-all mode 25 # m multi-line mode. 26 # ($ and ^ match at embedded new-lines) 27 # D Unix Lines mode (only recognize 0x0a as new-line) 34 # 2-9 a digit between 2 and 9, specifies the number of 42 # a Use non-Anchoring Bounds. 53 # Look-ahead expressions 55 "(?!0{5})(\d{5})" "<0><1>00001</1></0>zzzz" [all …]`
/external/cronet/stable/third_party/icu/source/test/testdata/
D	regextst.txt	`3 # Copyright (c) 2001-2015 International Business Machines 17 # if any, is group 0, as in <0>matched text</0> 24 # s dot-matches-all mode 25 # m multi-line mode. 26 # ($ and ^ match at embedded new-lines) 27 # D Unix Lines mode (only recognize 0x0a as new-line) 34 # 2-9 a digit between 2 and 9, specifies the number of 42 # a Use non-Anchoring Bounds. 53 # Look-ahead expressions 55 "(?!0{5})(\d{5})" "<0><1>00001</1></0>zzzz" [all …]`
/external/icu/icu4c/source/test/testdata/
D	regextst.txt	`3 # Copyright (c) 2001-2015 International Business Machines 17 # if any, is group 0, as in <0>matched text</0> 24 # s dot-matches-all mode 25 # m multi-line mode. 26 # ($ and ^ match at embedded new-lines) 27 # D Unix Lines mode (only recognize 0x0a as new-line) 34 # 2-9 a digit between 2 and 9, specifies the number of 42 # a Use non-Anchoring Bounds. 53 # Look-ahead expressions 55 "(?!0{5})(\d{5})" "<0><1>00001</1></0>zzzz" [all …]`
/external/strace/tests-m32/
D	net.expected	1 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +socket$AF_(LOCAL\|UNIX\|FILE), SOCK_STREAM, 0$ += 0 2 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +socket$AF_(LOCAL\|UNIX\|FILE), SOCK_STREAM, 0$ += 1 3 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +bind$0, \{sa_family=AF_(LOCAL\|UNIX\|FILE), sun_path="net… 4 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +listen\(0, 5$ += 0 5 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +getsockname\(0, \{sa_family=AF_(LOCAL\|UNIX\|FILE), sun_pa… 6 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +accept4?\(0, \{sa_family=AF_(LOCAL\|UNIX\|FILE)\}, \[19->2… 7 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +connect\(1, \{sa_family=AF_(LOCAL\|UNIX\|FILE), sun_path="…
/external/strace/tests/
D	net.expected	1 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +socket$AF_(LOCAL\|UNIX\|FILE), SOCK_STREAM, 0$ += 0 2 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +socket$AF_(LOCAL\|UNIX\|FILE), SOCK_STREAM, 0$ += 1 3 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +bind$0, \{sa_family=AF_(LOCAL\|UNIX\|FILE), sun_path="net… 4 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +listen\(0, 5$ += 0 5 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +getsockname\(0, \{sa_family=AF_(LOCAL\|UNIX\|FILE), sun_pa… 6 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +accept4?\(0, \{sa_family=AF_(LOCAL\|UNIX\|FILE)\}, \[19->2… 7 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +connect\(1, \{sa_family=AF_(LOCAL\|UNIX\|FILE), sun_path="…
/external/strace/tests-mx32/
D	net.expected	1 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +socket$AF_(LOCAL\|UNIX\|FILE), SOCK_STREAM, 0$ += 0 2 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +socket$AF_(LOCAL\|UNIX\|FILE), SOCK_STREAM, 0$ += 1 3 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +bind$0, \{sa_family=AF_(LOCAL\|UNIX\|FILE), sun_path="net… 4 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +listen\(0, 5$ += 0 5 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +getsockname\(0, \{sa_family=AF_(LOCAL\|UNIX\|FILE), sun_pa… 6 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +accept4?\(0, \{sa_family=AF_(LOCAL\|UNIX\|FILE)\}, \[19->2… 7 [1-9][0-9]* +[0-9]+:[0-9]+:[0-9]+\.[0-9]+ +connect\(1, \{sa_family=AF_(LOCAL\|UNIX\|FILE), sun_path="…

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toolchain
tools
trusty