| /external/coreboot/src/cpu/intel/turbo/ |
| D | turbo.c | 51 msr = rdmsr(IA32_MISC_ENABLE); in update_turbo_state()
96 msr = rdmsr(IA32_MISC_ENABLE); in enable_turbo()
98 wrmsr(IA32_MISC_ENABLE, msr); in enable_turbo()
115 msr = rdmsr(IA32_MISC_ENABLE); in disable_turbo()
117 wrmsr(IA32_MISC_ENABLE, msr); in disable_turbo()
|
| /external/coreboot/src/soc/intel/braswell/ |
| D | tsc_freq.c | 47 msr = rdmsr(IA32_MISC_ENABLE); in set_max_freq()
49 wrmsr(IA32_MISC_ENABLE, msr); in set_max_freq()
52 msr = rdmsr(IA32_MISC_ENABLE); in set_max_freq()
54 wrmsr(IA32_MISC_ENABLE, msr); in set_max_freq()
|
| /external/coreboot/src/soc/intel/denverton_ns/ |
| D | cpu.c | 85 msr = rdmsr(IA32_MISC_ENABLE); in configure_thermal_core()
87 wrmsr(IA32_MISC_ENABLE, msr); in configure_thermal_core()
103 msr = rdmsr(IA32_MISC_ENABLE); in denverton_core_init()
105 wrmsr(IA32_MISC_ENABLE, msr); in denverton_core_init()
113 msr = rdmsr(IA32_MISC_ENABLE); in denverton_core_init()
115 wrmsr(IA32_MISC_ENABLE, msr); in denverton_core_init()
|
| /external/coreboot/src/northbridge/intel/ironlake/ |
| D | early_init.c | 58 m = rdmsr(IA32_MISC_ENABLE); in early_cpu_init()
62 wrmsr(IA32_MISC_ENABLE, m); in early_cpu_init()
72 m = rdmsr(IA32_MISC_ENABLE); in early_cpu_init()
74 wrmsr(IA32_MISC_ENABLE, m); in early_cpu_init()
|
| /external/coreboot/src/cpu/intel/model_106cx/ |
| D | model_106cx_init.c | 44 msr = rdmsr(IA32_MISC_ENABLE); in configure_misc()
55 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
58 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
|
| /external/coreboot/src/soc/intel/xeon_sp/cpx/ |
| D | cpu.c | 98 msr = rdmsr(IA32_MISC_ENABLE); in each_cpu_init()
100 wrmsr(IA32_MISC_ENABLE, msr); in each_cpu_init()
106 msr = rdmsr(IA32_MISC_ENABLE); in each_cpu_init()
108 wrmsr(IA32_MISC_ENABLE, msr); in each_cpu_init()
|
| /external/coreboot/src/cpu/intel/model_6ex/ |
| D | model_6ex_init.c | 45 msr = rdmsr(IA32_MISC_ENABLE); in configure_misc()
62 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
65 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
|
| /external/coreboot/src/soc/intel/xeon_sp/skx/ |
| D | cpu.c | 122 msr = rdmsr(IA32_MISC_ENABLE); in xeon_sp_core_init()
124 wrmsr(IA32_MISC_ENABLE, msr); in xeon_sp_core_init()
137 msr = rdmsr(IA32_MISC_ENABLE); in xeon_sp_core_init()
139 wrmsr(IA32_MISC_ENABLE, msr); in xeon_sp_core_init()
|
| /external/coreboot/src/cpu/intel/model_6fx/ |
| D | model_6fx_init.c | 48 msr = rdmsr(IA32_MISC_ENABLE); in configure_misc()
70 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
73 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
|
| /external/coreboot/src/soc/intel/xeon_sp/spr/ |
| D | cpu.c | 131 msr = rdmsr(IA32_MISC_ENABLE); in each_cpu_init()
133 wrmsr(IA32_MISC_ENABLE, msr); in each_cpu_init()
139 msr = rdmsr(IA32_MISC_ENABLE); in each_cpu_init()
141 wrmsr(IA32_MISC_ENABLE, msr); in each_cpu_init()
|
| /external/coreboot/src/soc/intel/baytrail/ |
| D | tsc_freq.c | 42 msr = rdmsr(IA32_MISC_ENABLE); in set_max_freq()
44 wrmsr(IA32_MISC_ENABLE, msr); in set_max_freq()
|
| /external/coreboot/src/soc/intel/common/block/cpu/ |
| D | cpulib.c | 163 msr = rdmsr(IA32_MISC_ENABLE); in cpu_get_burst_mode_state()
219 msr = rdmsr(IA32_MISC_ENABLE); in cpu_burst_mode()
224 wrmsr(IA32_MISC_ENABLE, msr); in cpu_burst_mode()
236 msr = rdmsr(IA32_MISC_ENABLE); in cpu_set_eist()
241 wrmsr(IA32_MISC_ENABLE, msr); in cpu_set_eist()
|
| /external/coreboot/src/soc/intel/jasperlake/ |
| D | cpu.c | 47 msr = rdmsr(IA32_MISC_ENABLE); in configure_misc()
50 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
|
| /external/coreboot/src/soc/intel/tigerlake/ |
| D | cpu.c | 53 msr = rdmsr(IA32_MISC_ENABLE); in configure_misc()
56 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
|
| /external/coreboot/src/soc/intel/elkhartlake/ |
| D | cpu.c | 47 msr = rdmsr(IA32_MISC_ENABLE); in configure_misc()
50 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
|
| /external/coreboot/src/mainboard/acer/aspire_vn7_572g/ |
| D | smihandler.c | 32 msr_unset(IA32_MISC_ENABLE, 0x4000000000); in toggle_turbo_disable()
35 msr_set(IA32_MISC_ENABLE, 0x4000000000); in toggle_turbo_disable()
|
| /external/coreboot/src/soc/intel/meteorlake/ |
| D | cpu.c | 58 msr = rdmsr(IA32_MISC_ENABLE); in configure_misc()
61 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
|
| /external/coreboot/src/cpu/intel/model_2065x/ |
| D | model_2065x_init.c | 42 msr = rdmsr(IA32_MISC_ENABLE); in configure_misc()
46 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
|
| /external/coreboot/src/cpu/intel/model_1067x/ |
| D | model_1067x_init.c | 152 msr = rdmsr(IA32_MISC_ENABLE); in configure_misc()
182 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
186 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
|
| /external/coreboot/src/soc/intel/skylake/ |
| D | cpu.c | 59 msr = rdmsr(IA32_MISC_ENABLE); in configure_misc()
62 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
|
| /external/coreboot/src/soc/intel/cannonlake/ |
| D | cpu.c | 50 msr = rdmsr(IA32_MISC_ENABLE); in configure_misc()
53 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
|
| /external/coreboot/src/soc/intel/alderlake/ |
| D | cpu.c | 62 msr = rdmsr(IA32_MISC_ENABLE); in configure_misc()
65 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
|
| /external/coreboot/src/security/intel/txt/ |
| D | getsec_enteraccs.S | 63 PUSH_MSR IA32_MISC_ENABLE
315 POP_MSR IA32_MISC_ENABLE
|
| /external/crosvm/hypervisor/src/haxm/haxm_sys/ |
| D | msrs.rs | 42 pub const IA32_MISC_ENABLE: u32 = 0x1a0; constant
|
| /external/coreboot/src/cpu/intel/haswell/ |
| D | haswell_init.c | 469 msr = rdmsr(IA32_MISC_ENABLE); in configure_misc()
473 wrmsr(IA32_MISC_ENABLE, msr); in configure_misc()
|