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/external/tensorflow/tensorflow/python/autograph/operators/
Dlogical_test.py17 from tensorflow.python.autograph.operators import logical
35 self.assertTrue(logical.and_(lambda: True, lambda: True))
36 self.assertTrue(logical.and_(lambda: [1], lambda: True))
37 self.assertListEqual(logical.and_(lambda: True, lambda: [1]), [1])
39 self.assertFalse(logical.and_(lambda: False, lambda: True))
40 self.assertFalse(logical.and_(lambda: False, self.assertNotCalled))
45 t = logical.and_(self._tf_true, self._tf_true)
47 t = logical.and_(self._tf_true, lambda: True)
49 t = logical.and_(self._tf_false, lambda: True)
54 self.assertFalse(logical.or_(lambda: False, lambda: False))
[all …]
D__init__.py47 from tensorflow.python.autograph.operators.logical import and_
48 from tensorflow.python.autograph.operators.logical import eq
49 from tensorflow.python.autograph.operators.logical import not_
50 from tensorflow.python.autograph.operators.logical import not_eq
51 from tensorflow.python.autograph.operators.logical import or_
/external/iptables/extensions/
Dlibebt_standard.t16 --logical-in br0;=;OK
17 --logical-out br1;=;FAIL
21 --logical-in + -d 00:0f:ee:d0:ba:be;-d 00:0f:ee:d0:ba:be;OK
22 --logical-in + -p ip;-p IPv4;OK
23 ! --logical-in +;=;OK
27 --logical-in br0 --logical-out br1;=;OK
31 --logical-in br0;=;FAIL
32 --logical-out br1;=;OK
/external/tensorflow/tensorflow/lite/kernels/
Dlogical.cc27 namespace logical { namespace
136 static TfLiteRegistration r = {logical::Init, logical::Free, logical::Prepare, in Register_LOGICAL_OR()
137 logical::LogicalOrEval}; in Register_LOGICAL_OR()
144 static TfLiteRegistration r = {logical::Init, logical::Free, logical::Prepare, in Register_LOGICAL_AND()
145 logical::LogicalAndEval}; in Register_LOGICAL_AND()
/external/sdv/vsomeip/third_party/boost/mpl/doc/src/refmanual/
DMetafunctions-Logical.rst2 .. |logical| replace:: `logical`_ substdef
3 .. _`logical`: `Logical Operations`_ target
6 .. |logical operations| replace:: `logical operations`_
/external/angle/third_party/glslang/src/Test/baseResults/
Dtypes.frag.out10 0:35 logical-and ( temp bool)
17 0:36 logical-and ( temp bool)
18 0:36 logical-and ( temp bool)
19 0:36 logical-and ( temp bool)
40 0:37 logical-and ( temp bool)
41 0:37 logical-and ( temp bool)
42 0:37 logical-and ( temp bool)
43 0:37 logical-and ( temp bool)
44 0:37 logical-and ( temp bool)
73 0:38 logical-and ( temp bool)
[all …]
Dhlsl.logical.binary.vec.frag.out1 hlsl.logical.binary.vec.frag
19 0:12 logical-and ( temp 4-component vector of bool)
31 0:13 logical-or ( temp 4-component vector of bool)
43 0:15 logical-and ( temp 4-component vector of bool)
56 0:16 logical-or ( temp 4-component vector of bool)
69 0:18 logical-and ( temp 4-component vector of bool)
82 0:19 logical-or ( temp 4-component vector of bool)
98 0:22 logical-or ( temp 4-component vector of bool)
99 0:22 logical-or ( temp 4-component vector of bool)
100 0:22 logical-or ( temp 4-component vector of bool)
[all …]
/external/deqp-deps/glslang/Test/baseResults/
Dtypes.frag.out10 0:35 logical-and ( temp bool)
17 0:36 logical-and ( temp bool)
18 0:36 logical-and ( temp bool)
19 0:36 logical-and ( temp bool)
40 0:37 logical-and ( temp bool)
41 0:37 logical-and ( temp bool)
42 0:37 logical-and ( temp bool)
43 0:37 logical-and ( temp bool)
44 0:37 logical-and ( temp bool)
73 0:38 logical-and ( temp bool)
[all …]
Dhlsl.logical.binary.vec.frag.out1 hlsl.logical.binary.vec.frag
19 0:12 logical-and ( temp 4-component vector of bool)
31 0:13 logical-or ( temp 4-component vector of bool)
43 0:15 logical-and ( temp 4-component vector of bool)
56 0:16 logical-or ( temp 4-component vector of bool)
69 0:18 logical-and ( temp 4-component vector of bool)
82 0:19 logical-or ( temp 4-component vector of bool)
98 0:22 logical-or ( temp 4-component vector of bool)
99 0:22 logical-or ( temp 4-component vector of bool)
100 0:22 logical-or ( temp 4-component vector of bool)
[all …]
/external/libogg/doc/
Drfc3533.txt101 bitstreams, which are called "Logical Bitstreams". A logical
104 "Packets". The packets are created by the encoder of that logical
130 o framing for logical bitstreams.
132 o interleaving of different logical bitstreams.
153 for Ogg. Ogg supports framing and interleaving of logical
163 A physical Ogg bitstream consists of multiple logical bitstreams
165 from multiple logical bitstreams multiplexed at the page level. The
166 logical bitstreams are identified by a unique serial number in the
177 content or encoder of the logical bitstream it represents. Pages of
178 all logical bitstreams are concurrently interleaved, but they need
[all …]
/external/e2fsprogs/tests/f_yesall/
Dexpect3 (logical block 0, invalid physical block 999999999, len 1)
6 (logical block 1, invalid physical block 9999999999, len 1)
12 (logical block 1, invalid physical block 8888888888888, len 1)
16 (logical block 0, invalid physical block 888888888888, len 1)
23 (logical block 300, invalid physical block 777777777777, len 300)
27 (logical block 0, invalid physical block 7777777777, len 1)
/external/coreboot/src/soc/intel/skylake/
Dgpio.c9 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30},
10 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30},
11 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30},
15 { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30},
16 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30},
17 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30},
18 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30},
/external/coreboot/src/soc/intel/apollolake/
Dmeminit.c105 int logical; member
115 { .logical = LP4_SPEED_1600, .fsp_value = 0x9 },
116 { .logical = LP4_SPEED_2133, .fsp_value = 0xa },
117 { .logical = LP4_SPEED_2400, .fsp_value = 0xb },
126 { .logical = LP4_SPEED_1600, .fsp_value = 0x4 },
127 { .logical = LP4_SPEED_2133, .fsp_value = 0x6 },
128 { .logical = LP4_SPEED_2400, .fsp_value = 0x7 },
151 if (fsp_profile->mappings[i].logical == speed) in validate_speed()
166 if (fsp_profile->mappings[i].logical == speed) in fsp_memory_profile()
/external/e2fsprogs/tests/f_yesthenall/
Dexpect3 (logical block 0, invalid physical block 999999999, len 1)
6 (logical block 1, invalid physical block 9999999999, len 1)
10 (logical block 1, invalid physical block 8888888888888, len 1)
13 (logical block 0, invalid physical block 888888888888, len 1)
18 (logical block 300, invalid physical block 777777777777, len 300)
21 (logical block 0, invalid physical block 7777777777, len 1)
/external/cldr/docs/site/translation/getting-started/
Dresolving-errors.md7 A "logical group" is a set of _items_ that need to be treated as a single unit in terms of voting.
9 Examples of common logical groups in the survey tool data are:
14 All errors in logical groups must be resolved. All non-resolved errors must be resolved by the CLDR…
21 …1. This is most serious and it means that one or more items in what's considered as a logical grou…
22 1. To fix: Make sure that values for ALL of the items in the logical group are there.
23 …**all** of the month names. Once you enter values for all the items in a logical group, this error…
28 3. Error type 3: "**This item has a lower draft status (in its logical group) than X.**".
/external/coreboot/src/soc/intel/cannonlake/
Dgpio_cnp_h.c9 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
10 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
11 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
15 { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
16 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
17 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
18 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
Dgpio.c9 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
10 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
11 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
15 { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
16 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
17 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
18 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
/external/coreboot/src/soc/intel/jasperlake/
Dgpio.c9 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
10 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
11 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
15 { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
16 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
17 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
18 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
/external/e2fsprogs/tests/f_yes/
Dexpect3 (logical block 0, invalid physical block 999999999, len 1)
6 (logical block 1, invalid physical block 9999999999, len 1)
10 (logical block 1, invalid physical block 8888888888888, len 1)
13 (logical block 0, invalid physical block 888888888888, len 1)
18 (logical block 300, invalid physical block 777777777777, len 300)
21 (logical block 0, invalid physical block 7777777777, len 1)
/external/e2fsprogs/tests/f_yesthenno/
Dexpect3 (logical block 0, invalid physical block 999999999, len 1)
6 (logical block 1, invalid physical block 9999999999, len 1)
10 (logical block 1, invalid physical block 8888888888888, len 1)
13 (logical block 0, invalid physical block 888888888888, len 1)
18 (logical block 300, invalid physical block 777777777777, len 300)
21 (logical block 0, invalid physical block 7777777777, len 1)
/external/e2fsprogs/tests/f_no/
Dexpect3 (logical block 0, invalid physical block 999999999, len 1)
6 (logical block 1, invalid physical block 9999999999, len 1)
10 (logical block 1, invalid physical block 8888888888888, len 1)
13 (logical block 0, invalid physical block 888888888888, len 1)
19 (logical block 300, invalid physical block 777777777777, len 300)
22 (logical block 0, invalid physical block 7777777777, len 1)
/external/coreboot/src/soc/intel/elkhartlake/
Dgpio.c9 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
10 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
11 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
15 { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
16 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
17 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
18 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
/external/coreboot/src/soc/intel/tigerlake/
Dgpio_pch_h.c15 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
16 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
17 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
20 { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
21 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
22 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
23 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
Dgpio.c17 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 0U << 30 },
18 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
19 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
22 { .logical = PAD_CFG0_LOGICAL_RESET_PWROK, .chipset = 0U << 30 },
23 { .logical = PAD_CFG0_LOGICAL_RESET_DEEP, .chipset = 1U << 30 },
24 { .logical = PAD_CFG0_LOGICAL_RESET_PLTRST, .chipset = 2U << 30 },
25 { .logical = PAD_CFG0_LOGICAL_RESET_RSMRST, .chipset = 3U << 30 },
/external/coreboot/src/soc/intel/alderlake/
Dgpio_pch_s.c15 { .logical = PAD_RESET(RSMRST), .chipset = 0U << 30 },
16 { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 },
17 { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 },
20 { .logical = PAD_RESET(PWROK), .chipset = 0U << 30 },
21 { .logical = PAD_RESET(DEEP), .chipset = 1U << 30 },
22 { .logical = PAD_RESET(PLTRST), .chipset = 2U << 30 },
23 { .logical = PAD_RESET(RSMRST), .chipset = 3U << 30 },

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