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Searched refs:MRMDestReg (Results 1 – 14 of 14) sorted by relevance

/external/llvm/lib/Target/X86/
DX86InstrVMX.td36 def VMREAD64rr : I<0x78, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
40 def VMREAD32rr : I<0x78, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
DX86InstrInfo.td801 def MOV8rr : I<0x88, MRMDestReg, (outs GR8 :$dst), (ins GR8 :$src),
803 def MOV16rr : I<0x89, MRMDestReg, (outs GR16:$dst), (ins GR16:$src),
805 def MOV32rr : I<0x89, MRMDestReg, (outs GR32:$dst), (ins GR32:$src),
807 def MOV64rr : RI<0x89, MRMDestReg, (outs GR64:$dst), (ins GR64:$src),
922 def MOV8rr_NOREX : I<0x88, MRMDestReg,
948 def BT16rr : I<0xA3, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
951 def BT32rr : I<0xA3, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
954 def BT64rr : RI<0xA3, MRMDestReg, (outs), (ins GR64:$src1, GR64:$src2),
1010 def BTC16rr : I<0xBB, MRMDestReg, (outs), (ins GR16:$src1, GR16:$src2),
1012 def BTC32rr : I<0xBB, MRMDestReg, (outs), (ins GR32:$src1, GR32:$src2),
[all …]
DX86InstrSystem.td115 def MOV32rd : I<0x21, MRMDestReg, (outs GR32:$dst), (ins DEBUG_REG:$src),
117 def MOV64rd : I<0x21, MRMDestReg, (outs GR64:$dst), (ins DEBUG_REG:$src),
128 def MOV32rc : I<0x20, MRMDestReg, (outs GR32:$dst), (ins CONTROL_REG:$src),
130 def MOV64rc : I<0x20, MRMDestReg, (outs GR64:$dst), (ins CONTROL_REG:$src),
153 def MOV16rs : I<0x8C, MRMDestReg, (outs GR16:$dst), (ins SEGMENT_REG:$src),
155 def MOV32rs : I<0x8C, MRMDestReg, (outs GR32:$dst), (ins SEGMENT_REG:$src),
157 def MOV64rs : RI<0x8C, MRMDestReg, (outs GR64:$dst), (ins SEGMENT_REG:$src),
DX86InstrShiftRotate.td601 def SHLD16rrCL : I<0xA5, MRMDestReg, (outs GR16:$dst),
606 def SHRD16rrCL : I<0xAD, MRMDestReg, (outs GR16:$dst),
611 def SHLD32rrCL : I<0xA5, MRMDestReg, (outs GR32:$dst),
615 def SHRD32rrCL : I<0xAD, MRMDestReg, (outs GR32:$dst),
619 def SHLD64rrCL : RI<0xA5, MRMDestReg, (outs GR64:$dst),
624 def SHRD64rrCL : RI<0xAD, MRMDestReg, (outs GR64:$dst),
632 def SHLD16rri8 : Ii8<0xA4, MRMDestReg,
639 def SHRD16rri8 : Ii8<0xAC, MRMDestReg,
646 def SHLD32rri8 : Ii8<0xA4, MRMDestReg,
653 def SHRD32rri8 : Ii8<0xAC, MRMDestReg,
[all …]
DX86InstrInfo.h272 MRMDestReg = 3, enumerator
548 case X86II::MRMDestReg: in getMemoryOperandNo()
DX86InstrMMX.td147 def MMX_MOVD64grr : MMXI<0x7E, MRMDestReg, (outs), (ins GR32:$dst, VR64:$src),
158 def MMX_MOVD64from64rr : MMXRI<0x7E, MRMDestReg,
DX86InstrExtension.td144 def MOVZX64rr32 : I<0x89, MRMDestReg, (outs GR64:$dst), (ins GR32:$src),
DX86InstrSSE.td2896 def VMOVPDI2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2905 def MOVPDI2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins VR128:$src),
2914 def MOVPQIto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
2922 def MOVSDto64rr : RPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins FR64:$src),
2930 def VMOVSS2DIrr : VPDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
2936 def MOVSS2DIrr : PDI<0x7E, MRMDestReg, (outs GR32:$dst), (ins FR32:$src),
3097 def VMOVQd64rr : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
3100 def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src),
4094 def rr : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst),
4112 def VPEXTRBrr64 : SS4AIi8<0x14, MRMDestReg, (outs GR64:$dst),
[all …]
DX86MCCodeEmitter.cpp884 case X86II::MRMDestReg: in EncodeInstruction()
DX86CodeEmitter.cpp838 case X86II::MRMDestReg: { in emitInstruction()
DX86InstrFormats.td22 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
DX86InstrArithmetic.td604 dag outlist, list<dag> pattern, Format f = MRMDestReg>
620 SDPatternOperator opnode, Format f = MRMDestReg>
/external/llvm/test/TableGen/
DTargetInstrInfo.td49 def AddRegFrm : Format<2>; def MRMDestReg : Format<3>;
88 "mov $dst, $src", 0x88, MRMDestReg,
102 "and $dst, $src2", 0x20, MRMDestReg,
/external/llvm/utils/TableGen/
DX86RecognizableInstr.cpp47 MRMDestReg = 3, enumerator
133 if (form == X86Local::MRMDestReg || in needsModRMForDecode()
151 if (form == X86Local::MRMDestReg || in isRegFormat()
623 case X86Local::MRMDestReg: in emitInstructionSpecifier()