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Searched refs:OpSize (Results 1 – 18 of 18) sorted by relevance

/external/llvm/lib/Target/X86/
DX86InstrSystem.td59 def IRET16 : I<0xcf, RawFrm, (outs), (ins), "iretw", []>, OpSize;
73 "in{w}\t{%dx, %ax|%AX, %DX}", []>, OpSize;
83 "in{w}\t{$port, %ax|%AX, $port}", []>, OpSize;
93 "out{w}\t{%ax, %dx|%DX, %AX}", []>, OpSize;
103 "out{w}\t{%ax, $port|$port, %AX}", []>, OpSize;
109 def IN16 : I<0x6D, RawFrm, (outs), (ins), "ins{w}", []>, OpSize;
154 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
161 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
168 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
175 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize;
[all …]
DX86InstrShiftRotate.td25 [(set GR16:$dst, (shl GR16:$src1, CL))]>, OpSize;
41 [(set GR16:$dst, (shl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
55 "shl{w}\t$dst", []>, OpSize;
72 [(store (shl (loadi16 addr:$dst), CL), addr:$dst)]>, OpSize;
86 OpSize;
101 OpSize;
116 [(set GR16:$dst, (srl GR16:$src1, CL))]>, OpSize;
130 [(set GR16:$dst, (srl GR16:$src1, (i8 imm:$src2)))]>, OpSize;
144 [(set GR16:$dst, (srl GR16:$src1, (i8 1)))]>, OpSize;
161 OpSize;
[all …]
DX86InstrFormats.td88 class OpSize { bit hasOpSizePrefix = 1; }
281 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
292 !if(hasOpSizePrefix /* OpSize */, [HasSSE2], [HasSSE1]));
332 // PDI - SSE2 instructions with TB and OpSize prefixes.
333 // PDIi8 - SSE2 instructions with ImmT == Imm8 and TB and OpSize prefixes.
335 // VPDI - SSE2 instructions with TB and OpSize prefixes in AVX form.
346 : I<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
350 : Ii8<o, F, outs, ins, asm, pattern, SSEPackedDouble>, TB, OpSize,
359 OpSize, Requires<[HasAVX]>;
363 // S3I - SSE3 instructions with TB and OpSize prefixes.
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DX86InstrInfo.td604 "nop{w}\t$zero", []>, TB, OpSize;
629 OpSize;
632 OpSize;
634 OpSize;
638 def POPF16 : I<0x9D, RawFrm, (outs), (ins), "popf{w}", []>, OpSize;
645 OpSize;
648 OpSize;
650 OpSize;
657 "push{w}\t$imm", []>, OpSize;
661 def PUSHF16 : I<0x9C, RawFrm, (outs), (ins), "pushf{w}", []>, OpSize;
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DX86InstrVMX.td19 def INVEPT : I<0x80, RawFrm, (outs), (ins), "invept", []>, OpSize, T8;
21 def INVVPID : I<0x81, RawFrm, (outs), (ins), "invvpid", []>, OpSize, T8;
25 "vmclear\t$vmcs", []>, OpSize, TB;
DX86InstrSSE.td253 "movapd", SSEPackedDouble>, OpSize, VEX;
257 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
262 "movapd", SSEPackedDouble>, OpSize, VEX;
266 "movupd", SSEPackedDouble, 0>, OpSize, VEX;
270 "movapd", SSEPackedDouble>, TB, OpSize;
274 "movupd", SSEPackedDouble, 0>, TB, OpSize;
356 SSEPackedDouble>, TB, OpSize;
774 // SSE2 instructions without OpSize prefix
939 // SSE2 instructions without OpSize prefix
1163 "ucomisd", SSEPackedDouble>, OpSize, VEX;
[all …]
DX86InstrExtension.td17 "{cbtw|cbw}", []>, OpSize; // AX = signext(AL)
24 "{cwtd|cwd}", []>, OpSize; // DX:AX = signext(AX)
42 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
44 "movs{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
59 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
61 "movz{bw|x}\t{$src, $dst|$dst, $src}", []>, TB, OpSize;
DX86InstrArithmetic.td21 "lea{w}\t{$src|$dst}, {$dst|$src}", []>, OpSize;
59 []>, OpSize; // AX,DX = AX*GR16
83 []>, OpSize; // AX,DX = AX*[mem16]
100 OpSize; // AX,DX = AX*GR16
114 "imul{w}\t$src", []>, OpSize; // AX,DX = AX*[mem16]
133 (X86smul_flag GR16:$src1, GR16:$src2))]>, TB, OpSize;
151 TB, OpSize;
173 (X86smul_flag GR16:$src1, imm:$src2))]>, OpSize;
179 OpSize;
208 OpSize;
[all …]
DX86InstrControl.td29 []>, OpSize;
37 "lretw\t$amt", []>, OpSize;
113 "ljmp{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
121 "ljmp{w}\t{*}$dst", []>, OpSize;
158 "lcall{w}\t{$seg, $off|$off, $seg}", []>, OpSize;
164 "lcall{w}\t{*}$dst", []>, OpSize;
172 "callw\t$dst", []>, OpSize;
DX86InstrCMovSetCC.td24 (X86cmov GR16:$src1, GR16:$src2, CondNode, EFLAGS))]>,TB,OpSize;
42 CondNode, EFLAGS))]>, TB, OpSize;
DX86InstrMMX.td363 SSEPackedDouble>, TB, OpSize;
369 SSEPackedDouble>, TB, OpSize;
372 SSEPackedDouble>, TB, OpSize;
DX86InstrCompiler.td151 [(set GR16:$dst, 0)]>, OpSize;
188 OpSize;
248 [(X86rep_movs i16)]>, REP, OpSize;
264 [(X86rep_stos i16)]>, REP, OpSize;
565 []>, OpSize, LOCK;
644 "inc{w}\t$dst", []>, OpSize, LOCK;
657 "dec{w}\t$dst", []>, OpSize, LOCK;
685 [(X86cas addr:$ptr, GR16:$swap, 2)]>, TB, OpSize, LOCK;
713 TB, OpSize, LOCK;
DX86InstrInfo.h339 OpSize = 1 << 6, enumerator
DX86MCCodeEmitter.cpp446 if (TSFlags & X86II::OpSize) in EmitVEXOpcodePrefix()
736 if (TSFlags & X86II::OpSize) in EmitOpcodePrefix()
DX86CodeEmitter.cpp636 if (Desc->TSFlags & X86II::OpSize) in emitInstruction()
DX86ISelLowering.cpp2217 uint32_t OpSize = (VA.getLocVT().getSizeInBits()+7)/8; in LowerCall() local
2218 FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); in LowerCall()
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp7901 int64_t OpSize; in GatherAllAliases() local
7906 bool IsOpLoad = FindAliasInfo(Chain.getNode(), OpPtr, OpSize, in GatherAllAliases()
7915 OpPtr, OpSize, OpSrcValue, OpSrcValueOffset, in GatherAllAliases()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp2411 uint32_t OpSize = (Arg.getValueType().getSizeInBits()+7)/8; in CalculateTailCallArgDest() local
2412 int FI = MF.getFrameInfo()->CreateFixedObject(OpSize, Offset, true); in CalculateTailCallArgDest()