| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 716 SETULT, // 1 1 0 0 True if unordered or less than enumerator
742 return Code == SETUGT || Code == SETUGE || Code == SETULT || Code == SETULE; in isUnsignedIntSetCC()
|
| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 166 case FCmpInst::FCMP_ULT: FOC = ISD::SETLT; FPC = ISD::SETULT; break; in getFCmpCondCode()
193 case ICmpInst::ICMP_ULT: return ISD::SETULT; in getICmpCondCode()
|
| /external/llvm/lib/Target/Alpha/ |
| D | AlphaISelDAGToDAG.cpp | 314 case ISD::SETLT: case ISD::SETOLT: case ISD::SETULT: in Select()
337 case ISD::SETUEQ: case ISD::SETULT: case ISD::SETULE: in Select()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 1966 if ((Cond == ISD::SETULT && C1 == 2) || (Cond == ISD::SETUGT && C1 == 1)){ in SimplifySetCC()
1970 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
2083 case ISD::SETULT: in SimplifySetCC()
2105 case ISD::SETULT: in SimplifySetCC()
2250 (Cond == ISD::SETLE) ? ISD::SETLT : ISD::SETULT); in SimplifySetCC()
2253 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal) in SimplifySetCC()
2266 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MaxVal) in SimplifySetCC()
2270 if ((Cond == ISD::SETLT || Cond == ISD::SETULT) && C1 == MinVal+1) in SimplifySetCC()
2291 if (Cond == ISD::SETULT && in SimplifySetCC()
2382 isCondCodeLegal(ISD::SETULT, N0.getValueType())) in SimplifySetCC()
[all …]
|
| D | LegalizeIntegerTypes.cpp | 772 case ISD::SETULT: in PromoteSetCCOperands()
1382 Amt, NVBitsNode, ISD::SETULT); in ExpandShiftWithUnknownAmountBit()
1481 ISD::SETULT); in ExpandIntRes_ADDSUB()
1486 ISD::SETULT); in ExpandIntRes_ADDSUB()
1495 LoOps[0], LoOps[1], ISD::SETULT); in ExpandIntRes_ADDSUB()
2170 ISD::SETULT : ISD::SETUGT); in ExpandIntRes_UADDSUBO()
2430 case ISD::SETULT: LowCC = ISD::SETULT; break; in IntegerExpandSetCCOperands()
2467 CCCode == ISD::SETUGT || CCCode == ISD::SETULT))) { in IntegerExpandSetCCOperands()
|
| D | SelectionDAG.cpp | 251 case ISD::SETULT: in isSignedOp()
302 case ISD::SETOLT: Result = ISD::SETULT ; break; // SETULT & SETNE in getSetCCAndOperation()
1492 case ISD::SETULT: return getConstant(C1.ult(C2), VT); in FoldSetCC()
1544 case ISD::SETULT: return getConstant(R==APFloat::cmpUnordered || in FoldSetCC()
6005 case ISD::SETULT: return "setult"; in getOperationName()
|
| D | LegalizeFloatTypes.cpp | 659 case ISD::SETULT: in SoftenSetCCOperands()
|
| D | LegalizeDAG.cpp | 1965 case ISD::SETULT: CC1 = ISD::SETLT; CC2 = ISD::SETUO; Opc = ISD::OR; break; in LegalizeSetCCCondCode()
3525 ISD::SETULT : ISD::SETUGT)); in ExpandNode()
|
| /external/llvm/lib/Target/CellSPU/ |
| D | README.txt | 78 SETULT unimplemented
|
| D | SPUISelLowering.cpp | 2594 case ISD::SETULT: in LowerSETCC()
|
| /external/llvm/lib/Target/PTX/ |
| D | PTXInstrInfo.td | 710 defm SETPLTu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETULT, "lt">;
723 defm SETPLTu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETULT, "lt">;
736 defm SETPLTu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETULT, "lt">;
749 defm SETPLTf32 : PTX_SETP_FP<RegF32, "f32", SETULT, SETOLT, "lt">;
758 defm SETPLTf64 : PTX_SETP_FP<RegF64, "f64", SETULT, SETOLT, "lt">;
|
| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrFPU.td | 192 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETULT),
|
| D | MBlazeInstrInfo.td | 773 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETULT),
810 (i32 GPR:$T), (i32 GPR:$F), SETULT),
842 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETULT), bb:$T),
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 567 case ISD::SETULT: return PPC::PRED_LT; in getPredicateForSetCC()
603 case ISD::SETULT: return 0; in getCRIdxForSetCC()
|
| D | PPCISelLowering.cpp | 239 setCondCodeAction(ISD::SETULT, MVT::f32, Expand); in PPCTargetLowering()
240 setCondCodeAction(ISD::SETULT, MVT::f64, Expand); in PPCTargetLowering()
3569 case ISD::SETULT: in LowerSELECT_CC()
3591 case ISD::SETULT: in LowerSELECT_CC()
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 654 case ISD::SETULT: return SPCC::ICC_CS; in IntCondCCodeToICC()
678 case ISD::SETULT: return SPCC::FCC_UL; in FPCondCCodeToFCC()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 475 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
772 (setcc node:$lhs, node:$rhs, SETULT)>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 1011 case ISD::SETULT: return ARMCC::LO; in IntCCToARMCC()
1037 case ISD::SETULT: CondCode = ARMCC::LT; break; in FPCCToARMCC()
2623 case ISD::SETULT: in getARMCmp()
2626 CC = (CC == ISD::SETULT) ? ISD::SETULE : ISD::SETUGT; in getARMCmp()
2640 CC = (CC == ISD::SETULE) ? ISD::SETULT : ISD::SETUGE; in getARMCmp()
3420 case ISD::SETULT: Invert = true; Opc = ARMISD::VCGE; break; in LowerVSETCC()
3450 case ISD::SETULT: Swap = true; in LowerVSETCC()
6917 case ISD::SETULT: in PerformSELECT_CCCombine()
6922 IsUnordered = (CC == ISD::SETULT || CC == ISD::SETULE); in PerformSELECT_CCCombine()
|
| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 668 case ISD::SETULT: in EmitCmp()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 704 case ISD::SETULT: in EmitCMP()
|
| /external/llvm/lib/Target/Blackfin/ |
| D | BlackfinInstrInfo.td | 583 defm SETULT : SETCC<setult, setuge, "<", " (iu);">;
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 2936 case ISD::SETULT: return X86::COND_B; in TranslateX86CC()
2979 case ISD::SETULT: in TranslateX86CC()
7600 case ISD::SETULT: Swap = true; in LowerVSETCC()
7649 case ISD::SETULT: Swap = true; in LowerVSETCC()
11236 case ISD::SETULT: in PerformSELECTCombine()
11330 case ISD::SETULT: in PerformSELECTCombine()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 418 case ISD::SETULT: return Mips::FCOND_ULT; in FPCondCCodeToFCC()
|