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Searched refs:TRI (Results 1 – 25 of 136) sorted by relevance

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/external/llvm/lib/CodeGen/
DVirtRegRewriter.cpp69 const TargetRegisterInfo &TRI) { in substitutePhysReg() argument
71 MO.substPhysReg(Reg, TRI); in substitutePhysReg()
80 MI.addRegisterKilled(Reg, &TRI, /*AddIfNotFound=*/ true); in substitutePhysReg()
160 const TargetRegisterInfo *TRI; member in __anon15f5f4500311::AvailableSpills
179 : TRI(tri), TII(tii) { in AvailableSpills()
188 const TargetRegisterInfo *getRegInfo() const { return TRI; } in getRegInfo()
219 DEBUG(dbgs() << " in physreg " << TRI->getName(Reg) in addAvailable()
289 const TargetRegisterInfo *TRI, in ComputeReloadLoc() argument
327 for (const unsigned *Alias = TRI->getAliasSet(PhysReg); *Alias; ++Alias) in ComputeReloadLoc()
473 static void ResurrectConfirmedKill(unsigned Reg, const TargetRegisterInfo* TRI, in ResurrectConfirmedKill() argument
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DRegisterScavenging.cpp40 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in setUsed()
48 for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R) in isAliasUsed()
83 TRI = TM.getRegisterInfo(); in enterBasicBlock()
86 assert((NumPhysRegs == 0 || NumPhysRegs == TRI->getNumRegs()) && in enterBasicBlock()
91 NumPhysRegs = TRI->getNumRegs(); in enterBasicBlock()
95 ReservedRegs = TRI->getReservedRegs(MF); in enterBasicBlock()
99 const unsigned *CSRegs = TRI->getCalleeSavedRegs(); in enterBasicBlock()
113 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++) in addRegWithSubRegs()
119 for (const unsigned *R = TRI->getAliasSet(Reg); *R; R++) in addRegWithAliases()
202 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in forward()
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DRegisterClassInfo.cpp27 RegisterClassInfo::RegisterClassInfo() : Tag(0), MF(0), TRI(0), CalleeSaved(0) in RegisterClassInfo()
35 if (MF->getTarget().getRegisterInfo() != TRI) { in runOnMachineFunction()
36 TRI = MF->getTarget().getRegisterInfo(); in runOnMachineFunction()
37 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
42 const unsigned *CSR = TRI->getCalleeSavedRegs(MF); in runOnMachineFunction()
47 CSRNum.resize(TRI->getNumRegs(), 0); in runOnMachineFunction()
49 for (const unsigned *AS = TRI->getOverlaps(Reg); in runOnMachineFunction()
57 BitVector RR = TRI->getReservedRegs(*MF); in runOnMachineFunction()
105 dbgs() << ' ' << PrintReg(RCI.Order[I], TRI); in compute()
DAggressiveAntiDepBreaker.cpp123 TRI(MF.getTarget().getRegisterInfo()), in AggressiveAntiDepBreaker()
129 BitVector CPSet = TRI->getAllocatableSet(MF, CriticalPathRCs[i]); in AggressiveAntiDepBreaker()
139 dbgs() << " " << TRI->getName(r)); in AggressiveAntiDepBreaker()
149 State = new AggressiveAntiDepState(TRI->getNumRegs(), BB); in StartBlock()
160 for (const unsigned *Alias = TRI->getOverlaps(*I); in StartBlock()
176 for (const unsigned *Alias = TRI->getOverlaps(*I); in StartBlock()
189 for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) { in StartBlock()
192 for (const unsigned *Alias = TRI->getOverlaps(Reg); in StartBlock()
220 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
229 dbgs() << " " << TRI->getName(Reg) << "=g" << in Observe()
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DCriticalAntiDepBreaker.cpp34 TRI(MF.getTarget().getRegisterInfo()), in CriticalAntiDepBreaker()
36 Classes(TRI->getNumRegs(), static_cast<const TargetRegisterClass *>(0)), in CriticalAntiDepBreaker()
37 KillIndices(TRI->getNumRegs(), 0), in CriticalAntiDepBreaker()
38 DefIndices(TRI->getNumRegs(), 0) {} in CriticalAntiDepBreaker()
45 for (unsigned i = 0, e = TRI->getNumRegs(); i != e; ++i) { in StartBlock()
70 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { in StartBlock()
92 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { in StartBlock()
105 for (const unsigned *I = TRI->getCalleeSavedRegs(); *I; ++I) { in StartBlock()
113 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { in StartBlock()
133 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg) { in Observe()
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DVirtRegMap.cpp58 TRI = mf.getTarget().getRegisterInfo(); in runOnMachineFunction()
82 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(), in runOnMachineFunction()
83 E = TRI->regclass_end(); I != E; ++I) in runOnMachineFunction()
85 TRI->getAllocatableSet(mf, *I))); in runOnMachineFunction()
125 return TRI->ResolveRegAllocHint(Hint.first, physReg, *MF); in getRegAllocPref()
227 unsigned NumRegs = TRI->getNumRegs(); in FindUnusedRegisters()
238 BitVector Allocatable = TRI->getAllocatableSet(*MF); in FindUnusedRegisters()
243 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) { in FindUnusedRegisters()
298 PhysReg = TRI->getSubReg(PhysReg, MO.getSubReg()); in rewrite()
310 MI->addRegisterKilled(SuperKills.pop_back_val(), TRI, true); in rewrite()
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DLiveVariables.cpp193 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in FindLastPartialDef()
215 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
217 for (const unsigned *SubRegs = TRI->getSubRegisters(DefReg); in FindLastPartialDef()
248 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in HandlePhysRegUse()
260 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS) in HandlePhysRegUse()
273 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in HandlePhysRegUse()
289 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in FindLastRefOrPartRef()
338 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in HandlePhysRegKill()
353 for (const unsigned *SS = TRI->getSubRegisters(SubReg); *SS; ++SS) in HandlePhysRegKill()
368 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true); in HandlePhysRegKill()
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DRegAllocFast.cpp60 const TargetRegisterInfo *TRI; member in __anon4fc2f4500111::RAFast
219 LR.LastUse->addRegisterKilled(LR.PhysReg, TRI, true); in addKillFlag()
264 DEBUG(dbgs() << "Spilling " << PrintReg(LRI->first, TRI) in spillVirtReg()
265 << " in " << PrintReg(LR.PhysReg, TRI)); in spillVirtReg()
269 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI); in spillVirtReg()
346 for (const unsigned *AS = TRI->getAliasSet(PhysReg); in usePhysReg()
352 assert(TRI->isSuperRegister(PhysReg, Alias) && in usePhysReg()
357 MO.getParent()->addRegisterKilled(Alias, TRI, true); in usePhysReg()
360 if (TRI->isSuperRegister(PhysReg, Alias)) { in usePhysReg()
363 MO.getParent()->addRegisterKilled(Alias, TRI, true); in usePhysReg()
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DLocalStackSlotAllocation.cpp90 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); in runOnMachineFunction() local
95 if (!TRI->requiresVirtualBaseRegisters(MF) || LocalObjectCount == 0) in runOnMachineFunction()
206 const TargetRegisterInfo *TRI) { in lookupCandidateBaseReg() argument
213 if (TRI->isFrameOffsetLegal(MI, Offset)) in lookupCandidateBaseReg()
229 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); in insertFrameReferenceRegisters() local
293 if (TRI->needsFrameBaseReg(MI, LocalOffsets[FrameIdx])) { in insertFrameReferenceRegisters()
310 MI, TRI)) { in insertFrameReferenceRegisters()
320 int64_t InstrOffset = TRI->getFrameIndexInstrOffset(MI, idx); in insertFrameReferenceRegisters()
321 const TargetRegisterClass *RC = TRI->getPointerRegClass(); in insertFrameReferenceRegisters()
331 TRI->materializeFrameBaseRegister(Entry, BaseReg, FrameIdx, in insertFrameReferenceRegisters()
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DLowerSubregs.cpp34 const TargetRegisterInfo *TRI; member
60 const TargetRegisterInfo *TRI);
77 const TargetRegisterInfo *TRI) { in TransferDeadFlag() argument
80 if (MII->addRegisterDead(DstReg, TRI)) in TransferDeadFlag()
116 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
143 TransferDeadFlag(MI, DstSubReg, TRI); in LowerSubregToReg()
180 TransferDeadFlag(MI, DstMO.getReg(), TRI); in LowerCopy()
199 TRI = MF.getTarget().getRegisterInfo(); in runOnMachineFunction()
DInterferenceCache.cpp27 TRI = tri; in init()
28 PhysRegEntries.assign(TRI->getNumRegs(), 0); in init()
36 if (!Entries[E].valid(LIUArray, TRI)) in get()
51 Entries[E].reset(PhysReg, LIUArray, TRI, MF); in get()
70 const TargetRegisterInfo *TRI, in reset() argument
78 for (const unsigned *AS = TRI->getOverlaps(PhysReg); *AS; ++AS) { in reset()
92 const TargetRegisterInfo *TRI) { in valid() argument
94 for (const unsigned *AS = TRI->getOverlaps(PhysReg); *AS; ++AS, ++i) { in valid()
DMachineRegisterInfo.cpp20 MachineRegisterInfo::MachineRegisterInfo(const TargetRegisterInfo &TRI) { in MachineRegisterInfo() argument
23 UsedPhysRegs.resize(TRI.getNumRegs()); in MachineRegisterInfo()
26 PhysRegUseDefLists = new MachineOperand*[TRI.getNumRegs()]; in MachineRegisterInfo()
27 memset(PhysRegUseDefLists, 0, sizeof(MachineOperand*)*TRI.getNumRegs()); in MachineRegisterInfo()
187 const TargetRegisterInfo &TRI, in EmitLiveInCopies() argument
215 void MachineRegisterInfo::closePhysRegsUsed(const TargetRegisterInfo &TRI) { in closePhysRegsUsed() argument
218 for (const unsigned *SS = TRI.getSubRegisters(i); in closePhysRegsUsed()
DRegAllocBasic.cpp191 DEBUG(PhysReg2LiveUnion[PhysReg].print(dbgs(), TRI)); in verify()
209 TRI->getName(PhysReg) << "\n"; in verify()
233 TRI = &vrm.getTargetRegInfo(); in init()
239 const unsigned NumRegs = TRI->getNumRegs(); in init()
278 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign()
279 << " to " << PrintReg(PhysReg, TRI) << '\n'); in assign()
288 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) in unassign()
289 << " from " << PrintReg(PhysReg, TRI) << '\n'); in unassign()
370 for (const unsigned *AliasI = TRI->getOverlaps(PhysReg); *AliasI; ++AliasI) in checkPhysRegInterference()
388 TRI->getName(PhysReg) << " " << SpilledVReg << '\n'); in spillReg()
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DPrologEpilogInserter.cpp68 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); in runOnMachineFunction() local
71 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL; in runOnMachineFunction()
72 FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn); in runOnMachineFunction()
122 if (TRI->requiresRegisterScavenging(Fn) && FrameIndexVirtualScavenging) in runOnMachineFunction()
304 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo(); in insertCSRSpillsAndRestores() local
310 if (!TFI->spillCalleeSavedRegisters(*EntryBlock, I, CSI, TRI)) { in insertCSRSpillsAndRestores()
318 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
320 CSI[i].getFrameIdx(), RC, TRI); in insertCSRSpillsAndRestores()
342 if (!TFI->restoreCalleeSavedRegisters(*MBB, I, CSI, TRI)) { in insertCSRSpillsAndRestores()
345 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in insertCSRSpillsAndRestores()
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DLiveIntervalUnion.cpp81 LiveIntervalUnion::print(raw_ostream &OS, const TargetRegisterInfo *TRI) const { in print()
82 OS << "LIU " << PrintReg(RepReg, TRI); in print()
89 << PrintReg(SI.value()->reg, TRI); in print()
95 const TargetRegisterInfo *TRI) const { in print()
97 << PrintReg(interference()->reg, TRI); in print()
101 const TargetRegisterInfo *TRI) { in print() argument
103 LiveUnion->print(OS, TRI); in print()
107 IR.print(OS, TRI); in print()
DInterferenceCache.h22 const TargetRegisterInfo *TRI; variable
92 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
97 const TargetRegisterInfo *TRI,
127 InterferenceCache() : TRI(0), LIUArray(0), Indexes(0), MF(0), RoundRobin(0) {} in InterferenceCache()
DDeadMachineInstructionElim.cpp32 const TargetRegisterInfo *TRI; member in __anond5fe35450111::DeadMachineInstructionElim
88 TRI = MF.getTarget().getRegisterInfo(); in runOnMachineFunction()
92 BitVector ReservedRegs = TRI->getReservedRegs(MF); in runOnMachineFunction()
172 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in runOnMachineFunction()
186 for (const unsigned *AliasSet = TRI->getAliasSet(Reg); in runOnMachineFunction()
DAllocationOrder.cpp42 const TargetRegisterInfo &TRI = VRM.getTargetRegInfo(); in AllocationOrder() local
45 TRI.getRawAllocationOrder(RC, HintPair.first, Hint, in AllocationOrder()
60 Hint = TRI.ResolveRegAllocHint(HintPair.first, Hint, in AllocationOrder()
DTwoAddressInstructionPass.cpp63 const TargetRegisterInfo *TRI; member in __anon3ca1cbf20111::TwoAddressInstructionPass
266 KillMO = MI->findRegisterUseOperand(SavedReg, false, TRI); in Sink3AddrInstruction()
508 regsAreCompatible(unsigned RegA, unsigned RegB, const TargetRegisterInfo *TRI) { in regsAreCompatible() argument
513 return TRI->regsOverlap(RegA, RegB); in regsAreCompatible()
558 if ((FromRegB && ToRegB && !regsAreCompatible(FromRegB, ToRegB, TRI)) && in isProfitableToCommute()
560 regsAreCompatible(FromRegB, ToRegC, TRI) || in isProfitableToCommute()
561 regsAreCompatible(FromRegC, ToRegB, TRI))) in isProfitableToCommute()
634 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI)); in isProfitableToConv3Addr()
651 if (NewMI->findRegisterUseOperand(RegB, false, TRI)) in ConvertInstTo3Addr()
947 TII->getRegClass(UnfoldMCID, LoadRegIndex, TRI); in TryInstructionTransform()
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DTargetInstrInfoImpl.cpp168 const TargetRegisterInfo &TRI) const { in reMaterialize()
170 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI); in reMaterialize()
281 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo(); in foldMemoryOperand() local
284 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI); in foldMemoryOperand()
286 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI); in foldMemoryOperand()
325 const TargetRegisterInfo &TRI = *TM.getRegisterInfo(); in isReallyTriviallyReMaterializableGeneric() local
368 BitVector AllocatableRegs = TRI.getAllocatableSet(MF, 0); in isReallyTriviallyReMaterializableGeneric()
372 for (const unsigned *Alias = TRI.getAliasSet(Reg); *Alias; ++Alias) { in isReallyTriviallyReMaterializableGeneric()
/external/llvm/include/llvm/CodeGen/
DMachineInstr.h312 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
313 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
333 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
334 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
341 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
342 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
348 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
349 return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1;
356 const TargetRegisterInfo *TRI = NULL) const {
357 return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1;
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/external/llvm/lib/Target/
DTargetRegisterInfo.cpp39 else if (TRI && Reg < TRI->getNumRegs()) in print()
40 OS << '%' << TRI->getName(Reg); in print()
44 if (TRI) in print()
45 OS << ':' << TRI->getSubRegIndexName(SubIdx); in print()
/external/llvm/lib/Target/ARM/
DThumb2ITBlockPass.cpp33 const TargetRegisterInfo *TRI; member in __anon07555c0b0111::Thumb2ITBlockPass
58 const TargetRegisterInfo *TRI) { in TrackDefUses() argument
78 for (const unsigned *Subreg = TRI->getSubRegisters(Reg); in TrackDefUses()
86 for (const unsigned *Subreg = TRI->getSubRegisters(Reg); in TrackDefUses()
160 TrackDefUses(MI, Defs, Uses, TRI); in InsertITInstructions()
206 TrackDefUses(NMI, Defs, Uses, TRI); in InsertITInstructions()
230 TRI = TM.getRegisterInfo(); in runOnMachineFunction()
DThumb2InstrInfo.h50 const TargetRegisterInfo *TRI) const;
56 const TargetRegisterInfo *TRI) const;
61 const TargetRegisterInfo &TRI) const;
DARMExpandPseudoInsts.cpp39 const TargetRegisterInfo *TRI; member in __anonf70e727b0111::ARMExpandPseudo
380 const TargetRegisterInfo *TRI, unsigned &D0, in GetDSubRegs() argument
383 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
384 D1 = TRI->getSubReg(Reg, ARM::dsub_1); in GetDSubRegs()
385 D2 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
386 D3 = TRI->getSubReg(Reg, ARM::dsub_3); in GetDSubRegs()
388 D0 = TRI->getSubReg(Reg, ARM::dsub_0); in GetDSubRegs()
389 D1 = TRI->getSubReg(Reg, ARM::dsub_2); in GetDSubRegs()
390 D2 = TRI->getSubReg(Reg, ARM::dsub_4); in GetDSubRegs()
391 D3 = TRI->getSubReg(Reg, ARM::dsub_6); in GetDSubRegs()
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