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Searched refs:getOperand (Results 1 – 25 of 367) sorted by relevance

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/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp37 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
38 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
39 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); in EmitAnyX86InstComments()
43 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
44 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
49 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
50 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
55 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
58 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
59 DecodePSHUFMask(4, MI->getOperand(MI->getNumOperands()-1).getImm(), in EmitAnyX86InstComments()
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/external/llvm/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp26 Constant *Op0 = C->getOperand(0); in CheapToScalarize()
28 if (C->getOperand(i) != Op0) in CheapToScalarize()
38 isa<ConstantInt>(I->getOperand(2))) in CheapToScalarize()
44 (CheapToScalarize(BO->getOperand(0), isConstant) || in CheapToScalarize()
45 CheapToScalarize(BO->getOperand(1), isConstant))) in CheapToScalarize()
49 (CheapToScalarize(CI->getOperand(0), isConstant) || in CheapToScalarize()
50 CheapToScalarize(CI->getOperand(1), isConstant))) in CheapToScalarize()
60 if (isa<ConstantAggregateZero>(SVI->getOperand(2))) in getShuffleMask()
62 if (isa<UndefValue>(SVI->getOperand(2))) in getShuffleMask()
66 const ConstantVector *CP = cast<ConstantVector>(SVI->getOperand(2)); in getShuffleMask()
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DInstCombineShifts.cpp22 assert(I.getOperand(1)->getType() == I.getOperand(0)->getType()); in commonShiftTransforms()
23 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in commonShiftTransforms()
91 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
94 return CanEvaluateTruncated(I->getOperand(0), Ty); in CanEvaluateShifted()
111 return CanEvaluateShifted(I->getOperand(0), NumBits, isLeftShift, IC) && in CanEvaluateShifted()
112 CanEvaluateShifted(I->getOperand(1), NumBits, isLeftShift, IC); in CanEvaluateShifted()
116 CI = dyn_cast<ConstantInt>(I->getOperand(1)); in CanEvaluateShifted()
131 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
140 CI = dyn_cast<ConstantInt>(I->getOperand(1)); in CanEvaluateShifted()
155 if (MaskedValueIsZero(I->getOperand(0), in CanEvaluateShifted()
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DInstCombineSelect.cpp31 LHS = ICI->getOperand(0); in MatchSelectPattern()
32 RHS = ICI->getOperand(1); in MatchSelectPattern()
35 if (SI->getTrueValue() == ICI->getOperand(0) && in MatchSelectPattern()
36 SI->getFalseValue() == ICI->getOperand(1)) { in MatchSelectPattern()
51 if (SI->getTrueValue() == ICI->getOperand(1) && in MatchSelectPattern()
52 SI->getFalseValue() == ICI->getOperand(0)) { in MatchSelectPattern()
129 if (TI->getOperand(0)->getType() != FI->getOperand(0)->getType()) in FoldSelectOpOp()
136 Value *NewSI = Builder->CreateSelect(SI.getCondition(), TI->getOperand(0), in FoldSelectOpOp()
137 FI->getOperand(0), SI.getName()+".v"); in FoldSelectOpOp()
149 if (TI->getOperand(0) == FI->getOperand(0)) { in FoldSelectOpOp()
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DInstCombineAndOrXor.cpp198 Value *X = Op->getOperand(0); in OptAndOp()
322 Value *ShVal = Op->getOperand(0); in OptAndOp()
412 !isa<ConstantInt>(LHSI->getOperand(1))) return 0; in FoldLogicalPlusAnd()
414 ConstantInt *N = cast<ConstantInt>(LHSI->getOperand(1)); in FoldLogicalPlusAnd()
449 return Builder->CreateSub(LHSI->getOperand(0), RHS, "fold"); in FoldLogicalPlusAnd()
450 return Builder->CreateAdd(LHSI->getOperand(0), RHS, "fold"); in FoldLogicalPlusAnd()
572 if (LHS->getOperand(0)->getType() != RHS->getOperand(0)->getType()) return 0; in foldLogOpOfMaskedICmpsHelper()
574 if (LHS->getOperand(0)->getType()->isVectorTy()) return 0; in foldLogOpOfMaskedICmpsHelper()
582 Value *L1 = LHS->getOperand(0); in foldLogOpOfMaskedICmpsHelper()
583 Value *L2 = LHS->getOperand(1); in foldLogOpOfMaskedICmpsHelper()
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DInstCombineCasts.cpp41 if (ConstantInt *RHS = dyn_cast<ConstantInt>(I->getOperand(1))) { in DecomposeSimpleLinearExpr()
46 return I->getOperand(0); in DecomposeSimpleLinearExpr()
53 return I->getOperand(0); in DecomposeSimpleLinearExpr()
61 DecomposeSimpleLinearExpr(I->getOperand(0), SubScale, Offset); in DecomposeSimpleLinearExpr()
110 DecomposeSimpleLinearExpr(AI.getOperand(0), ArraySizeScale, ArrayOffset); in PromoteCastOfAllocation()
180 Value *LHS = EvaluateInDifferentType(I->getOperand(0), Ty, isSigned); in EvaluateInDifferentType()
181 Value *RHS = EvaluateInDifferentType(I->getOperand(1), Ty, isSigned); in EvaluateInDifferentType()
191 if (I->getOperand(0)->getType() == Ty) in EvaluateInDifferentType()
192 return I->getOperand(0); in EvaluateInDifferentType()
196 Res = CastInst::CreateIntegerCast(I->getOperand(0), Ty, in EvaluateInDifferentType()
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DInstCombineCompares.cpp213 !isa<ConstantInt>(GEP->getOperand(1)) || in FoldCmpLoadFromIndexedGlobal()
214 !cast<ConstantInt>(GEP->getOperand(1))->isZero() || in FoldCmpLoadFromIndexedGlobal()
215 isa<Constant>(GEP->getOperand(2))) in FoldCmpLoadFromIndexedGlobal()
225 ConstantInt *Idx = dyn_cast<ConstantInt>(GEP->getOperand(i)); in FoldCmpLoadFromIndexedGlobal()
273 Constant *CompareRHS = cast<Constant>(ICI.getOperand(1)); in FoldCmpLoadFromIndexedGlobal()
275 Constant *Elt = Init->getOperand(i); in FoldCmpLoadFromIndexedGlobal()
359 Value *Idx = GEP->getOperand(2); in FoldCmpLoadFromIndexedGlobal()
481 if (ConstantInt *CI = dyn_cast<ConstantInt>(GEP->getOperand(i))) { in EvaluateGEPOffsetExpression()
502 Value *VariableIdx = GEP->getOperand(i); in EvaluateGEPOffsetExpression()
509 ConstantInt *CI = dyn_cast<ConstantInt>(GEP->getOperand(i)); in EvaluateGEPOffsetExpression()
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DInstCombineMulDivRem.cpp49 isPowerOfTwo(I->getOperand(0), IC.getTargetData())) { in simplifyValueKnownNonZero()
52 if (Value *V2 = simplifyValueKnownNonZero(I->getOperand(0), IC)) { in simplifyValueKnownNonZero()
101 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitMul()
117 if (Constant *ShOp = dyn_cast<Constant>(SI->getOperand(1))) in visitMul()
118 return BinaryOperator::CreateMul(SI->getOperand(0), in visitMul()
192 (BO->getOperand(1) == Op1C || BO->getOperand(1) == Neg) && in visitMul()
195 Value *Op0BO = BO->getOperand(0), *Op1BO = BO->getOperand(1); in visitMul()
257 Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1); in visitFMul()
297 SelectInst *SI = cast<SelectInst>(I.getOperand(1)); in SimplifyDivRemOfSelect()
301 if (Constant *ST = dyn_cast<Constant>(SI->getOperand(1))) in SimplifyDivRemOfSelect()
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DInstCombineSimplifyDemanded.cpp33 ConstantInt *OpC = dyn_cast<ConstantInt>(I->getOperand(OpNo)); in ShrinkDemandedConstant()
159 ComputeMaskedBits(I->getOperand(1), DemandedMask, in SimplifyDemandedUseBits()
161 ComputeMaskedBits(I->getOperand(0), DemandedMask & ~RHSKnownZero, in SimplifyDemandedUseBits()
169 return I->getOperand(0); in SimplifyDemandedUseBits()
172 return I->getOperand(1); in SimplifyDemandedUseBits()
183 ComputeMaskedBits(I->getOperand(1), DemandedMask, in SimplifyDemandedUseBits()
185 ComputeMaskedBits(I->getOperand(0), DemandedMask & ~RHSKnownOne, in SimplifyDemandedUseBits()
193 return I->getOperand(0); in SimplifyDemandedUseBits()
196 return I->getOperand(1); in SimplifyDemandedUseBits()
202 return I->getOperand(0); in SimplifyDemandedUseBits()
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DInstCombineLoadStoreAlloca.cpp92 User *CI = cast<User>(LI.getOperand(0)); in InstCombineLoadCast()
93 Value *CastOp = CI->getOperand(0); in InstCombineLoadCast()
145 Value *Op = LI.getOperand(0); in visitLoadInst()
178 const Value *GEPI0 = GEPI->getOperand(0); in visitLoadInst()
223 if (isSafeToLoadUnconditionally(SI->getOperand(1), SI, Align, TD) && in visitLoadInst()
224 isSafeToLoadUnconditionally(SI->getOperand(2), SI, Align, TD)) { in visitLoadInst()
225 LoadInst *V1 = Builder->CreateLoad(SI->getOperand(1), in visitLoadInst()
226 SI->getOperand(1)->getName()+".val"); in visitLoadInst()
227 LoadInst *V2 = Builder->CreateLoad(SI->getOperand(2), in visitLoadInst()
228 SI->getOperand(2)->getName()+".val"); in visitLoadInst()
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/external/llvm/lib/Target/XCore/
DXCoreISelDAGToDAG.cpp100 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) in SelectADDRspii()
101 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRspii()
115 Base = Addr.getOperand(0); in SelectADDRdpii()
121 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper) in SelectADDRdpii()
122 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRdpii()
125 Base = Addr.getOperand(0).getOperand(0); in SelectADDRdpii()
136 Base = Addr.getOperand(0); in SelectADDRcpii()
142 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper) in SelectADDRcpii()
143 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRcpii()
146 Base = Addr.getOperand(0).getOperand(0); in SelectADDRcpii()
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/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp42 const MCOperand &Dst = MI->getOperand(0); in printInst()
43 const MCOperand &MO1 = MI->getOperand(1); in printInst()
44 const MCOperand &MO2 = MI->getOperand(2); in printInst()
45 const MCOperand &MO3 = MI->getOperand(3); in printInst()
70 MI->getOperand(0).getReg() == ARM::SP) { in printInst()
82 MI->getOperand(0).getReg() == ARM::SP) { in printInst()
94 MI->getOperand(0).getReg() == ARM::SP) { in printInst()
104 MI->getOperand(0).getReg() == ARM::SP) { in printInst()
114 unsigned BaseReg = MI->getOperand(0).getReg(); in printInst()
116 if (MI->getOperand(i).getReg() == BaseReg) in printInst()
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/external/llvm/lib/Target/CellSPU/
DSPUAsmPrinter.cpp64 const MachineOperand &MO = MI->getOperand(OpNo); in printOperand()
85 unsigned int value = MI->getOperand(OpNo).getImm(); in printU7ImmOperand()
93 char value = MI->getOperand(OpNo).getImm(); in printShufAddr()
103 O << (short) MI->getOperand(OpNo).getImm(); in printS16ImmOperand()
109 O << (unsigned short)MI->getOperand(OpNo).getImm(); in printU16ImmOperand()
117 const MachineOperand &MO = MI->getOperand(OpNo); in printMemRegReg()
125 unsigned int value = MI->getOperand(OpNo).getImm(); in printU18ImmOperand()
133 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16) in printS10ImmOperand()
143 short value = (short) (((int) MI->getOperand(OpNo).getImm() << 16) in printU10ImmOperand()
152 assert(MI->getOperand(OpNo).isImm() && in printDFormAddr()
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/external/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp36 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
37 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
38 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
66 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
67 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
87 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
112 char Value = MI->getOperand(OpNo).getImm(); in printS5ImmOperand()
119 unsigned char Value = MI->getOperand(OpNo).getImm(); in printU5ImmOperand()
126 unsigned char Value = MI->getOperand(OpNo).getImm(); in printU6ImmOperand()
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/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp389 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) in isNegatibleForFree()
392 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); in isNegatibleForFree()
405 if (char V = isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) in isNegatibleForFree()
408 return isNegatibleForFree(Op.getOperand(1), LegalOperations, Depth+1); in isNegatibleForFree()
413 return isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1); in isNegatibleForFree()
422 if (Op.getOpcode() == ISD::FNEG) return Op.getOperand(0); in GetNegatedExpression()
440 if (isNegatibleForFree(Op.getOperand(0), LegalOperations, Depth+1)) in GetNegatedExpression()
442 GetNegatedExpression(Op.getOperand(0), DAG, in GetNegatedExpression()
444 Op.getOperand(1)); in GetNegatedExpression()
447 GetNegatedExpression(Op.getOperand(1), DAG, in GetNegatedExpression()
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DLegalizeFloatTypes.cpp107 return BitConvertToInteger(N->getOperand(0)); in SoftenFloatRes_BITCAST()
115 BitConvertToInteger(N->getOperand(0)), in SoftenFloatRes_BUILD_PAIR()
116 BitConvertToInteger(N->getOperand(1))); in SoftenFloatRes_BUILD_PAIR()
126 SDValue NewOp = BitConvertVectorToIntegerVector(N->getOperand(0)); in SoftenFloatRes_EXTRACT_VECTOR_ELT()
129 NewOp, N->getOperand(1)); in SoftenFloatRes_EXTRACT_VECTOR_ELT()
140 SDValue Op = GetSoftenedFloat(N->getOperand(0)); in SoftenFloatRes_FABS()
146 SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), in SoftenFloatRes_FADD()
147 GetSoftenedFloat(N->getOperand(1)) }; in SoftenFloatRes_FADD()
158 SDValue Op = GetSoftenedFloat(N->getOperand(0)); in SoftenFloatRes_FCEIL()
168 SDValue LHS = GetSoftenedFloat(N->getOperand(0)); in SoftenFloatRes_FCOPYSIGN()
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DLegalizeIntegerTypes.cpp141 SDValue Op = SExtPromotedInteger(N->getOperand(0)); in PromoteIntRes_AssertSext()
143 Op.getValueType(), Op, N->getOperand(1)); in PromoteIntRes_AssertSext()
148 SDValue Op = ZExtPromotedInteger(N->getOperand(0)); in PromoteIntRes_AssertZext()
150 Op.getValueType(), Op, N->getOperand(1)); in PromoteIntRes_AssertZext()
154 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); in PromoteIntRes_Atomic1()
166 SDValue Op2 = GetPromotedInteger(N->getOperand(2)); in PromoteIntRes_Atomic2()
167 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); in PromoteIntRes_Atomic2()
178 SDValue InOp = N->getOperand(0); in PromoteIntRes_BITCAST()
212 GetSplitVector(N->getOperand(0), Lo, Hi); in PromoteIntRes_BITCAST()
236 SDValue Op = GetPromotedInteger(N->getOperand(0)); in PromoteIntRes_BSWAP()
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DLegalizeTypesGeneric.cpp38 SDValue InOp = N->getOperand(0); in ExpandRes_BITCAST()
148 Lo = N->getOperand(0); in ExpandRes_BUILD_PAIR()
149 Hi = N->getOperand(1); in ExpandRes_BUILD_PAIR()
154 GetExpandedOp(N->getOperand(0), Lo, Hi); in ExpandRes_EXTRACT_ELEMENT()
155 SDValue Part = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue() ? in ExpandRes_EXTRACT_ELEMENT()
166 SDValue OldVec = N->getOperand(0); in ExpandRes_EXTRACT_VECTOR_ELT()
181 SDValue Idx = N->getOperand(1); in ExpandRes_EXTRACT_VECTOR_ELT()
242 SDValue Chain = N->getOperand(0); in ExpandRes_VAARG()
243 SDValue Ptr = N->getOperand(1); in ExpandRes_VAARG()
247 Lo = DAG.getVAArg(NVT, dl, Chain, Ptr, N->getOperand(2), Align); in ExpandRes_VAARG()
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/external/llvm/lib/Target/Sparc/
DSparcISelDAGToDAG.cpp85 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) { in SelectADDRri()
88 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) { in SelectADDRri()
92 Base = Addr.getOperand(0); in SelectADDRri()
98 if (Addr.getOperand(0).getOpcode() == SPISD::Lo) { in SelectADDRri()
99 Base = Addr.getOperand(1); in SelectADDRri()
100 Offset = Addr.getOperand(0).getOperand(0); in SelectADDRri()
103 if (Addr.getOperand(1).getOpcode() == SPISD::Lo) { in SelectADDRri()
104 Base = Addr.getOperand(0); in SelectADDRri()
105 Offset = Addr.getOperand(1).getOperand(0); in SelectADDRri()
121 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRrr()
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/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp307 && isInt32Immediate(N->getOperand(1).getNode(), Imm); in isOpcWithIntImmediate()
343 !isInt32Immediate(N->getOperand(1).getNode(), Shift) || (Shift > 31)) in isRotateAndMask()
376 SDValue Op0 = N->getOperand(0); in SelectBitfieldInsert()
377 SDValue Op1 = N->getOperand(1); in SelectBitfieldInsert()
397 if (Op0.getOperand(0).getOpcode() == ISD::SHL || in SelectBitfieldInsert()
398 Op0.getOperand(0).getOpcode() == ISD::SRL) { in SelectBitfieldInsert()
399 if (Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
400 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
407 if (Op1Opc == ISD::AND && Op1.getOperand(0).getOpcode() != ISD::SHL && in SelectBitfieldInsert()
408 Op1.getOperand(0).getOpcode() != ISD::SRL) { in SelectBitfieldInsert()
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/external/llvm/lib/Target/ARM/
DARMMCCodeEmitter.cpp154 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); in getLdStmModeOpValue()
216 return MI.getOperand(Op).getReg() == ARM::CPSR; in getCCOutOpValue()
222 unsigned SoImm = MI.getOperand(Op).getImm(); in getSOImmOpValue()
238 unsigned SoImm = MI.getOperand(Op).getImm(); in getT2SOImmOpValue()
261 switch (MI.getOperand(Op).getImm()) { in getRotImmOpValue()
272 return MI.getOperand(Op).getImm() - 1; in getImmMinusOneOpValue()
277 return 64 - MI.getOperand(Op).getImm(); in getNEONVcvtImm32OpValue()
433 const MCOperand &MO = MI.getOperand(OpIdx); in EncodeAddrModeOpValues()
434 const MCOperand &MO1 = MI.getOperand(OpIdx + 1); in EncodeAddrModeOpValues()
460 const MCOperand &MO = MI.getOperand(OpIdx); in getBranchTargetOpValue()
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DARMBaseInstrInfo.cpp146 const MachineOperand &WB = isLoad ? MI->getOperand(1) : MI->getOperand(0); in convertToThreeAddress()
147 const MachineOperand &Base = MI->getOperand(2); in convertToThreeAddress()
148 const MachineOperand &Offset = MI->getOperand(NumOps-3); in convertToThreeAddress()
152 unsigned OffImm = MI->getOperand(NumOps-2).getImm(); in convertToThreeAddress()
153 ARMCC::CondCodes Pred = (ARMCC::CondCodes)MI->getOperand(NumOps-1).getImm(); in convertToThreeAddress()
206 get(MemOpc), MI->getOperand(0).getReg()) in convertToThreeAddress()
210 get(MemOpc)).addReg(MI->getOperand(1).getReg()) in convertToThreeAddress()
217 get(MemOpc), MI->getOperand(0).getReg()) in convertToThreeAddress()
221 get(MemOpc)).addReg(MI->getOperand(1).getReg()) in convertToThreeAddress()
224 UpdateMI->getOperand(0).setIsDead(); in convertToThreeAddress()
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DARMISelDAGToDAG.cpp287 isInt32Immediate(N->getOperand(1).getNode(), Imm); in isOpcWithIntImmediate()
382 BaseReg = N.getOperand(0); in SelectShifterOperandReg()
384 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { in SelectShifterOperandReg()
388 ShReg = N.getOperand(1); in SelectShifterOperandReg()
415 N.getOperand(0).getOpcode() == ISD::TargetGlobalAddress)) { in SelectAddrModeImm12()
416 Base = N.getOperand(0); in SelectAddrModeImm12()
423 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { in SelectAddrModeImm12()
429 Base = N.getOperand(0); in SelectAddrModeImm12()
451 if (ConstantSDNode *RHS = dyn_cast<ConstantSDNode>(N.getOperand(1))) { in SelectLdStSOReg()
463 Base = Offset = N.getOperand(0); in SelectLdStSOReg()
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/external/llvm/lib/MC/MCDisassembler/
DEDOperand.cpp138 result = Inst.Inst->getOperand(MCOpIndex).getImm(); in evaluate()
142 unsigned reg = Inst.Inst->getOperand(MCOpIndex).getReg(); in evaluate()
147 int64_t displacement = Inst.Inst->getOperand(MCOpIndex).getImm(); in evaluate()
162 unsigned baseReg = Inst.Inst->getOperand(MCOpIndex).getReg(); in evaluate()
163 uint64_t scaleAmount = Inst.Inst->getOperand(MCOpIndex+1).getImm(); in evaluate()
164 unsigned indexReg = Inst.Inst->getOperand(MCOpIndex+2).getReg(); in evaluate()
165 int64_t displacement = Inst.Inst->getOperand(MCOpIndex+3).getImm(); in evaluate()
169 unsigned segmentReg = Inst.Inst->getOperand(MCOpIndex+4).getReg(); in evaluate()
210 if (!Inst.Inst->getOperand(MCOpIndex).isImm()) in evaluate()
213 result = Inst.Inst->getOperand(MCOpIndex).getImm(); in evaluate()
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/external/llvm/lib/CodeGen/
DLowerSubregs.cpp96 MachineOperand &MO = MI->getOperand(i); in TransferImplicitDefs()
105 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg()
106 MI->getOperand(1).isImm() && in LowerSubregToReg()
107 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
108 MI->getOperand(3).isImm() && "Invalid subreg_to_reg"); in LowerSubregToReg()
110 unsigned DstReg = MI->getOperand(0).getReg(); in LowerSubregToReg()
111 unsigned InsReg = MI->getOperand(2).getReg(); in LowerSubregToReg()
112 assert(!MI->getOperand(2).getSubReg() && "SubIdx on physreg?"); in LowerSubregToReg()
113 unsigned SubIdx = MI->getOperand(3).getImm(); in LowerSubregToReg()
140 MI->getOperand(2).isKill()); in LowerSubregToReg()
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