/external/llvm/include/llvm/CodeGen/ |
D | MachineOperand.h | 176 bool isReg() const { return OpKind == MO_Register; } in isReg() function 207 assert(isReg() && "This is not a register operand!"); in getReg() 212 assert(isReg() && "Wrong MachineOperand accessor"); in getSubReg() 217 assert(isReg() && "Wrong MachineOperand accessor"); in isUse() 222 assert(isReg() && "Wrong MachineOperand accessor"); in isDef() 227 assert(isReg() && "Wrong MachineOperand accessor"); in isImplicit() 232 assert(isReg() && "Wrong MachineOperand accessor"); in isDead() 237 assert(isReg() && "Wrong MachineOperand accessor"); in isKill() 242 assert(isReg() && "Wrong MachineOperand accessor"); in isUndef() 247 assert(isReg() && "Wrong MachineOperand accessor"); in isEarlyClobber() [all …]
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D | LiveVariables.h | 226 if (MO.isReg() && MO.isKill() && MO.getReg() == reg) { in removeVirtualRegisterKilled() 261 if (MO.isReg() && MO.isDef() && MO.getReg() == reg) { in removeVirtualRegisterDead()
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/external/llvm/lib/CodeGen/ |
D | MachineInstr.cpp | 53 assert(isReg() && "Can only add reg operand to use lists"); in AddRegOperandToRegInfo() 144 if (isReg() && getParent() && getParent()->getParent() && in ChangeToImmediate() 160 if (isReg()) { in ChangeToRegister() 569 assert((!Operands[i].isReg() || !Operands[i].isOnRegUseList()) && in ~MachineInstr() 589 if (Operands[i].isReg()) in RemoveRegOperandsFromUseLists() 599 if (Operands[i].isReg()) in AddRegOperandsToUseLists() 610 bool isImpReg = Op.isReg() && Op.isImplicit(); in addOperand() 628 if (Op.isReg()) { in addOperand() 651 if (Operands[OpNo].isReg()) { in addOperand() 668 assert(Operands[i].isReg() && "Should only be an implicit reg!"); in addOperand() [all …]
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D | DeadMachineInstructionElim.cpp | 71 if (MO.isReg() && MO.isDef()) { in isDead() 136 if (!MO.isReg() || !MO.isDef()) in runOnMachineFunction() 165 if (MO.isReg() && MO.isDef()) { in runOnMachineFunction() 182 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
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D | TargetInstrInfoImpl.cpp | 64 if (HasDef && !MI->getOperand(0).isReg()) in commuteInstruction() 75 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && in commuteInstruction() 129 if (!MI->getOperand(SrcOpIdx1).isReg() || in findCommutedOpIndices() 130 !MI->getOperand(SrcOpIdx2).isReg()) in findCommutedOpIndices() 147 if (MO.isReg()) { in PredicateInstruction() 355 if (!MO.isReg()) continue; in isReallyTriviallyReMaterializableGeneric()
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D | MachineLICM.cpp | 373 if (!MO.isReg()) in ProcessMI() 477 if (!MO.isReg() || MO.isDef() || !MO.getReg()) in HoistRegionPostRA() 507 if (!MO.isReg() || !MO.getReg() || MO.isDef()) continue; in AddToLiveIns() 621 if (!MO.isReg() || MO.isImplicit()) in InitRegPressure() 654 if (!MO.isReg() || MO.isImplicit()) in UpdateRegPressure() 711 if (!MO.isReg()) in IsLoopInvariantInst() 800 if (!MO.isReg() || !MO.isUse()) in HasHighOperandLatency() 829 if (!DefMO.isReg() || !DefMO.isDef()) in IsCheapInstruction() 876 if (!MO.isReg() || MO.isImplicit()) in UpdateBackTraceRegPressure() 939 if (!MO.isReg() || MO.isImplicit()) in IsProfitableToHoist() [all …]
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D | ProcessImplicitDefs.cpp | 137 if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef()) in runOnMachineFunction() 172 if (MOJ.isReg() && MOJ.isUse() && MOJ.getReg() == Reg) in runOnMachineFunction() 185 if (!MO.isReg() || !MO.isDef()) in runOnMachineFunction() 249 if (RRMO.isReg() && RRMO.getReg() == Reg) { in runOnMachineFunction() 275 if (RRMO.isReg() && RRMO.getReg() == Reg) { in runOnMachineFunction()
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D | MachineCSE.cpp | 116 if (!MO.isReg() || !MO.isUse()) in PerformTrivialCoalescing() 166 if (!MO.isReg() || !MO.getReg()) in isPhysDefTriviallyDead() 196 if (!MO.isReg()) in hasLivePhysRegDefUses() 237 if (!MO.isReg() || !MO.isDef()) in PhysRegDefsReach() 302 if (MO.isReg() && MO.isUse() && in isProfitableToCSE() 427 if (!MO.isReg() || !MO.isDef()) in ProcessBlock()
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D | LowerSubregs.cpp | 97 if (!MO.isReg() || !MO.isImplicit() || MO.isUse()) in TransferImplicitDefs() 105 assert((MI->getOperand(0).isReg() && MI->getOperand(0).isDef()) && in LowerSubregToReg() 107 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
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D | RegisterScavenging.cpp | 157 if (!MO.isReg()) in forward() 184 if (!MO.isReg()) in forward() 288 if (!MO.isReg() || MO.isUndef() || !MO.getReg()) in findSurvivorReg() 339 if (MO.isReg() && MO.getReg() != 0 && in scavengeRegister()
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D | TwoAddressInstructionPass.cpp | 190 if (!MO.isReg()) in Sink3AddrInstruction() 244 if (!MO.isReg()) in Sink3AddrInstruction() 286 if (MO.isReg() && MO.getReg() == Reg && in isTwoAddrUse() 451 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse() 773 if (!MO.isReg()) in isSafeToDelete() 983 if (MO.isReg() && in TryInstructionTransform() 1093 assert(mi->getOperand(SrcIdx).isReg() && in runOnMachineFunction() 1159 !mi->getOperand(i).isReg() || in runOnMachineFunction() 1190 assert(MO.isReg() && MO.getReg() == regB && MO.isUse() && in runOnMachineFunction() 1204 if (MO.isReg() && MO.getReg() == regB && MO.isUse()) { in runOnMachineFunction() [all …]
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D | RegAllocFast.cpp | 655 if (!MO.isReg()) continue; in handleThroughOperands() 671 if (!MO.isReg() || !MO.isDef()) continue; in handleThroughOperands() 688 if (!MO.isReg()) continue; in handleThroughOperands() 720 if (!MO.isReg() || (MO.isDef() && !MO.isEarlyClobber())) continue; in handleThroughOperands() 815 if (!MO.isReg()) continue; in AllocateBasicBlock() 880 if (!MO.isReg()) continue; in AllocateBasicBlock() 930 if (!MO.isReg()) continue; in AllocateBasicBlock() 950 if (!MO.isReg()) continue; in AllocateBasicBlock() 980 if (!MO.isReg() || !MO.isDef() || !MO.getReg() || MO.isEarlyClobber()) in AllocateBasicBlock()
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D | CriticalAntiDepBreaker.cpp | 204 if (!MO.isReg()) continue; in PrescanInstruction() 256 if (!MO.isReg()) continue; in ScanInstruction() 291 if (!MO.isReg()) continue; in ScanInstruction() 358 if (!CheckOper.isReg() || !CheckOper.isDef() || in isNewRegClobberedByRefs() 585 if (!MO.isReg()) continue; in BreakAntiDependencies()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCMCCodeEmitter.cpp | 90 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getDirectBrEncoding() 101 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getCondBrEncoding() 112 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getHA16Encoding() 123 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getLO16Encoding() 135 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding() 153 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding() 180 if (MO.isReg()) { in getMachineOpValue()
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D | PPCCodeEmitter.cpp | 182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getDirectBrEncoding() 198 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getHA16Encoding() 207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getLO16Encoding() 217 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIEncoding() 233 assert(MI.getOperand(OpNo+1).isReg()); in getMemRIXEncoding() 248 if (MO.isReg()) { in getMachineOpValue()
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/external/llvm/lib/CodeGen/AsmPrinter/ |
D | AsmPrinterDwarf.cpp | 217 if (Dst.isReg() && Dst.getReg() == MachineLocation::VirtualFP) { in EmitCFIFrameMove() 225 } else if (Src.isReg() && Src.getReg() == MachineLocation::VirtualFP) { in EmitCFIFrameMove() 226 assert(Dst.isReg() && "Machine move not supported yet."); in EmitCFIFrameMove() 229 assert(!Dst.isReg() && "Machine move not supported yet."); in EmitCFIFrameMove()
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/external/llvm/lib/Target/X86/ |
D | X86MCCodeEmitter.cpp | 482 if (!MI.getOperand(i).isReg()) in EmitVEXOpcodePrefix() 506 if (MI.getNumOperands() > CurOp && MI.getOperand(CurOp).isReg() && in EmitVEXOpcodePrefix() 528 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg())) in EmitVEXOpcodePrefix() 530 if (!VEX_B && MO.isReg() && in EmitVEXOpcodePrefix() 540 if (MI.getOperand(CurOp).isReg() && in EmitVEXOpcodePrefix() 550 if (MO.isReg() && !HasVEX_4V && in EmitVEXOpcodePrefix() 605 if (!MO.isReg()) continue; in DetermineREXPrefix() 617 if (MI.getOperand(0).isReg() && in DetermineREXPrefix() 623 if (MO.isReg() && X86InstrInfo::isX86_64ExtendedReg(MO.getReg())) in DetermineREXPrefix() 628 if (MI.getOperand(0).isReg() && in DetermineREXPrefix() [all …]
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D | SSEDomainFix.cpp | 311 if (!mo.isReg()) continue; in visitHardInstr() 320 if (!mo.isReg()) continue; in visitHardInstr() 340 if (!mo.isReg()) continue; in visitSoftInstr() 424 if (!mo.isReg()) continue; in visitSoftInstr() 438 if (!mo.isReg()) continue; in visitGenericInstr()
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D | X86MCInstLower.cpp | 208 if (!MI->getOperand(OpNo+i).isReg()) continue; in lower_lea64_32mem() 233 assert(Inst.getOperand(0).isReg() && Inst.getOperand(ImmOp).isImm() && in SimplifyShortImmForm() 234 ((Inst.getNumOperands() == 3 && Inst.getOperand(1).isReg() && in SimplifyShortImmForm() 258 bool IsStore = Inst.getOperand(0).isReg() && Inst.getOperand(1).isReg(); in SimplifyShortMoveForm() 262 assert(Inst.getNumOperands() == 6 && Inst.getOperand(RegOp).isReg() && in SimplifyShortMoveForm() 263 Inst.getOperand(AddrBase + 0).isReg() && // base in SimplifyShortMoveForm() 265 Inst.getOperand(AddrBase + 2).isReg() && // index register in SimplifyShortMoveForm() 268 Inst.getOperand(AddrBase + 4).isReg() && // segment in SimplifyShortMoveForm()
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D | X86InstrInfo.h | 602 MI->getOperand(Op ).isReg() && isScale(MI->getOperand(Op+1)) && in isLeaMem() 603 MI->getOperand(Op+2).isReg() && in isLeaMem() 613 MI->getOperand(Op+4).isReg() && in isMem() 838 if (!MO.isReg()) return false; in isX86_64ExtendedReg()
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/external/llvm/include/llvm/MC/ |
D | MCInst.h | 52 bool isReg() const { return Kind == kRegister; } in isReg() function 59 assert(isReg() && "This is not a register operand!"); in getReg() 65 assert(isReg() && "This is not a register operand!"); in setReg()
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/external/llvm/lib/Target/MBlaze/ |
D | MBlazeDelaySlotFiller.cpp | 137 bool aop_is_reg = a->getOperand(aop).isReg(); in delayHasHazard() 145 bool mop_is_reg = m->getOperand(mop).isReg(); in delayHasHazard() 165 if (a->getOperand(aop).isReg()) { in delayHasHazard() 169 if (b->getOperand(bop).isReg() && !b->getOperand(bop).isImplicit()) { in delayHasHazard()
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/external/llvm/lib/Target/Sparc/ |
D | DelaySlotFiller.cpp | 213 if (!MO.isReg()) in delayHasHazard() 244 assert(Reg.isReg() && "JMPL first operand is not a register."); in insertCallUses() 251 assert(RegOrImm.isReg() && "JMPLrr second operand is not a register."); in insertCallUses() 265 if (!MO.isReg()) in insertDefsUses()
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D | SparcAsmPrinter.cpp | 75 if (MI->getOpcode() == SP::SETHIi && !MO.isReg() && !MO.isImm()) { in printOperand() 79 !MO.isReg() && !MO.isImm()) { in printOperand() 121 if (MI->getOperand(opNum+1).isReg() && in printMemOperand()
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/external/llvm/lib/Target/CellSPU/ |
D | SPUAsmPrinter.cpp | 65 if (MO.isReg()) { in printOperand() 308 if (!MI->getOperand(OpNo).isReg() || in PrintAsmOperand() 310 !MI->getOperand(OpNo+1).isReg()) in PrintAsmOperand()
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