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/external/bouncycastle/src/main/java/org/bouncycastle/crypto/engines/
DRC2Engine.java209 int x76, x54, x32, x10; in encryptBlock() local
214 x10 = ((in[inOff + 1] & 0xff) << 8) + (in[inOff + 0] & 0xff); in encryptBlock()
218 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
219 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
220 x54 = rotateWordLeft(x54 + (x76 & ~x32) + (x10 & x32) + workingKey[i+2], 3); in encryptBlock()
221 x76 = rotateWordLeft(x76 + (x10 & ~x54) + (x32 & x54) + workingKey[i+3], 5); in encryptBlock()
224 x10 += workingKey[x76 & 63]; in encryptBlock()
225 x32 += workingKey[x10 & 63]; in encryptBlock()
231 x10 = rotateWordLeft(x10 + (x32 & ~x76) + (x54 & x76) + workingKey[i ], 1); in encryptBlock()
232 x32 = rotateWordLeft(x32 + (x54 & ~x10) + (x76 & x10) + workingKey[i+1], 2); in encryptBlock()
[all …]
/external/dropbear/libtomcrypt/src/ciphers/
Drc2.c141 unsigned x76, x54, x32, x10, i; in _rc2_ecb_encrypt() local
152 x10 = ((unsigned)pt[1] << 8) + (unsigned)pt[0]; in _rc2_ecb_encrypt()
155 x10 = (x10 + (x32 & ~x76) + (x54 & x76) + xkey[4*i+0]) & 0xFFFF; in _rc2_ecb_encrypt()
156 x10 = ((x10 << 1) | (x10 >> 15)); in _rc2_ecb_encrypt()
158 x32 = (x32 + (x54 & ~x10) + (x76 & x10) + xkey[4*i+1]) & 0xFFFF; in _rc2_ecb_encrypt()
161 x54 = (x54 + (x76 & ~x32) + (x10 & x32) + xkey[4*i+2]) & 0xFFFF; in _rc2_ecb_encrypt()
164 x76 = (x76 + (x10 & ~x54) + (x32 & x54) + xkey[4*i+3]) & 0xFFFF; in _rc2_ecb_encrypt()
168 x10 = (x10 + xkey[x76 & 63]) & 0xFFFF; in _rc2_ecb_encrypt()
169 x32 = (x32 + xkey[x10 & 63]) & 0xFFFF; in _rc2_ecb_encrypt()
175 ct[0] = (unsigned char)x10; in _rc2_ecb_encrypt()
[all …]
/external/oprofile/events/x86-64/family10/
Dunit_masks40 0x10 (M)odified cache state
47 0x10 Modified-state line from L2
54 0x10 Multiply pipe load ops and SSE move ops
62 0x10 FS register
83 0x10 DCT1 Page miss
93 0x10 DCT1 Read to write turnaround
108 0x10 Read byte (4 bytes)
115 0x10 Upstream display refresh/ISOC reads
124 0x10 Canceled request
139 0x10 DEV hit
[all …]
/external/oprofile/events/x86-64/family11h/
Dunit_masks29 0x10 (M)odified cache state
36 0x10 (M)odified cache state from L2
43 0x10 Multiply pipe load ops
50 0x10 FS register
79 0x10 DCT1 Page miss
93 0x10 DCT1 Write to read turnaround
102 0x10 Read byte (4 bytes)
109 0x10 Upstream display refresh/ISOC reads
118 0x10 Cancelled request
127 0x10 DEV hit
[all …]
/external/stlport/stlport/
Dcomplex22 # define _STLP_OUTERMOST_HEADER_ID 0x10
27 #if (_STLP_OUTERMOST_HEADER_ID == 0x10)
40 #if (_STLP_OUTERMOST_HEADER_ID != 0x10) || defined (_STLP_IMPORT_VENDOR_STD)
48 #if (_STLP_OUTERMOST_HEADER_ID == 0x10 )
/external/oprofile/events/i386/westmere/
Dunit_masks14 name:x10 type:mandatory default:0x10
15 0x10 No unit mask
33 0x10 direct_near_call Unconditional call branches executed
48 0x10 direct_near_call Mispredicted non call branches executed
67 0x10 stlb_hit DTLB second level hit
74 0x10 stlb_hit DTLB first level misses but second level hit
86 0x10 sse_fp_packed SSE FP packed Uops
135 0x10 prefetch_i_state L2 data prefetches in the I state (misses)
158 0x10 ifetch_hit L2 instruction fetch hits
171 0x10 l1d_wb L1D writeback to L2 transactions
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dthumb-tests.txt28 0x10 0xf1 0x1f 0x0f
49 0xf7 0xe9 0x10 0x01
79 0x0c 0xf3 0x10 0x00
82 0xc7 0xe9 0x10 0x01
213 0x15 0xf8 0x10 0xf0
216 0x1f 0xf8 0x10 0xf0
234 0x1 0x10
237 0x4f 0xea 0x10 0x0a
/external/oprofile/events/i386/core_2/
Dunit_masks11 name:x10 type:mandatory default:0x10
12 0x10 No unit mask
42 0x10 SIMD packed logical
56 0x10 UNTIL_RETIRE Loads blocked until retirement.
84 0x10 prefetch: Hardware prefetch only
97 0x10 prefetch: Hardware prefetch only
127 0x10 ITLB large page misses
166 0x10 Retired SSE2 vector integer instructions
178 0x10 Retired loads that miss the DTLB (precise event)
195 0x10 due to branch misprediction
/external/llvm/test/MC/Disassembler/MBlaze/
Dmblaze_fpu.txt8 0x58 0x01 0x10 0x00
11 0x58 0x01 0x10 0x80
32 0x58 0x01 0x12 0x10
Dmblaze_imm.txt23 0x20 0x00 0x00 0x10
47 0x20 0x00 0x10 0x00
77 0xb0 0x00 0x00 0x10 0x20 0x00 0x00 0x00
109 0xb0 0x00 0x10 0x00 0x20 0x00 0x00 0x00
Dmblaze_operands.txt14 0x00 0x42 0x10 0x00
56 0x02 0x10 0x80 0x00
119 0x20 0x00 0x00 0x10
143 0x20 0x00 0x10 0x00
/external/v8/test/mjsunit/regress/
Dregress-969.js117 x10 = 0;
118 function test10(index) { return first((++o[index], typeof x10), 2); }
120 delete x10;
Dregress-r4998.js48 var x10 = 3;
64 x10 = 266;
/external/oprofile/events/i386/core/
Dunit_masks27 0x10 HW prefetched line only
28 0x20 all prefetched line w/o regarding mask 0x10.
31 0x10 Intel(tm) Enhanced SpeedStep(r) Technology frequency transitions
50 0x10 MMX packed logical
/external/sonivox/jet_tools/JetCreator/
Dimg_Paste.py13 \xa6\x1bk^\xa1\x8fS\xb5\x08\x18\x10\x03c\x07\x84X\x902\xb6o\x90\x951\xdd\xca\
19 \xfe\x1c\xa0,\x05{\x8dF\xe7\x10\xc2\xab\rLd\xb0\xd9\x14\xcd\x00\x8e\xc9\x18\
22 \x9b\x80\xf5ZBJ\xde\xdd\xc2\xba\x08\x93\xe4\xcdv\x08\x0f\x80\xf3\xf7\x00\x10\
23 E\xbc\x13\x8f\x88X\xe9\xb2\x9e\x81,\xcbm\x87t\x0b\xd0\xe4Pb\x01\x10\x91\xf5e\
Dimg_Redo.py13 \x12JK+\xb4bE\x8a .mR7\x12\x16\x83\x0eBb\x9a\x10\x83\xf1\x05\xa1\xf0\xe2\x93\
24 \xc3.\xcfJ\x10\xf9uy\xd1C\x9e\x9a\x05+rK\xf2KI\xae\xa7\x10~=\x1f\x94\xa8\x18\
25 Nv\x81I\x1bB\xda`\xd2\x86\x97\xe6B\x85\x1f\xdf\x9d=\x10\x8f\xc6\xa2\xad\xf3\
33 \x07\x80\x1c\xb5\x18\xb6\xcd\x10\x1e\x0b1\x10\x1ct\x8a\xdf\x15 \xf0\x85g\xd5\
34 \xfc95k\xea\x17\xadS\xa2v\x10\x00 \x89\n@\xa6?H\xcfR#\xe0\xa6\xd9\x97>\xa3D\
39 C\xdfH\xa7\x0c\x86{\x93c\xb1\x90\x88L\x84\xfdo\xae}\x87J)\x10\xb2\xae\x02\
Dimg_Save.py37 \x9egNw\xdexfL\\\x10\x8bW\xaf^\xcdko\xf7\xf1\x8d\x1f\xbdy\x89\xdbl["\x84\xc0\
52 6_\x16`\xd9\xb2e\xb6\x10\xe2\x91\x8e\x8e\x0e\xf2\xf9<\xb6mc\x8cA)E\x10\x04\
58 \xc9$\xf3\xe7\xcfo\xee\xeb\xeb[}\t\x80\x10\xe2\xabk\xd6\xac!\x97\xcb\x01\x10\
68 \xc4C\x1d\x1d\x1d\xb8\xaeKmm-\xd9l\x96\xb1\xb11\x84\x10\x04A\x10\xf6-\xcb"\
81 \x10\xc0\x18s\xf2\xd4\xa9SM7\xdf|s\x988\xa5\xe4)\xf5\xaf&uuuh\xadioo\xc7\xf3\
83 \x8e\x02q\x1b\xc0u\xddoo\xdf\xbe}\xbbeY\xf5W\xf5\xfb5hA\x10\x0cd2\x99\xe7\
Dimg_Cut.py22 \x82%\xc5K,6E{k2\x00;\xf7\xd4lp:\x93\xf2rsr\xa9\x10\x12\xc5\xc5\xc5v\x9b\xa2\
33 \x92$|\x83\xc1\xe1-\xe9\x19\xe9\xa9n\xf7=\x10B\x80\x10\x82\x8b\x17[\xcch,\
56 \x1d\x12@\xdf\xd0\x10\xda|>X\xdc\xb6\xa8?6r\xc4\x19\x10\xdf\x0e:\xc9{\x19\
61 \x94ZU\xb4uv\x07\xb8\x10$\xc5\xe9$3\xb3\xb3\x1d\x94R4]\xb8\x1029\xafz\xd84o:\
67 \x8b(\x8a\x02Hy\xd3\xda\xf9\xf1\x10\x02jDr]\xd7\x117\x0c\x85\x00\'\xd7\x01W\
70 \x08\nc\xed\xb7N\x9dBY\xbb\xce,p\xdal\xa6\x00V&\x9e\x97\x01\xd7\x98\x10\xcb\
75 \x93\x18;\x90\x99\x9a\xea\xd24\r>\xbf\xdf0\x84\xf8\xe5m\x19\x10\xe2\x17\xdd~\
/external/oprofile/events/x86-64/hammer/
Dunit_masks23 0x10 (M)odified cache state
30 0x10 (M)odified cache state from L2
37 0x10 Multiply pipe load ops
44 0x10 FS register
86 0x10 Read byte (4 bytes)
94 0x10 Upstream display refresh reads
107 0x10 Cancelled request
122 0x10 32-byte Sized Reads (RevD and later)
159 0x10 Read Block Modified (Dcache store miss refill)
/external/oprofile/events/i386/p4/
Dunit_masks33 0x10 replay cause: partial overlap between load and store
40 0x10 read 3rd level cache hit exclusive
50 0x10 bus request type bit 4
80 0x10 handle x87 input assist
109 0x10 count indirect jumps
121 0x10 count when other reserves bus and this processor will sample
127 0x10 count all x87 SIMD load uops
/external/oprofile/events/i386/p6_mobile/
Dunit_masks11 0x10 HW prefetched line only
12 0x20 all prefetched line w/o regarding mask 0x10.
35 0x10 MMX packed logical
/external/oprofile/events/x86-64/family12h/
Dunit_masks22 0x10 (M)odified cache state
29 0x10 Modified-state line from L2
/external/oprofile/events/x86-64/family14h/
Dunit_masks22 0x10 (M)odified cache state
29 0x10 Modified-state line from L2
/external/oprofile/events/i386/p4-ht/
Dunit_masks33 0x10 replay cause: partial overlap between load and store
40 0x10 read 3rd level cache hit exclusive
50 0x10 handle x87 input assist
79 0x10 count indirect jumps
/external/skia/src/core/
DSkFilterProc.h24 unsigned x10, unsigned x11);
69 uint32_t x10, uint32_t x11);

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