| /external/llvm/lib/CodeGen/ |
| D | Analysis.cpp | 160 case FCmpInst::FCMP_ONE: FOC = ISD::SETNE; FPC = ISD::SETONE; break; in getFCmpCondCode()
168 case FCmpInst::FCMP_UNE: FOC = ISD::SETNE; FPC = ISD::SETUNE; break; in getFCmpCondCode()
187 case ICmpInst::ICMP_NE: return ISD::SETNE; in getICmpCondCode()
198 return ISD::SETNE; in getICmpCondCode()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | TargetLowering.cpp | 527 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
528 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
537 CCs[RTLIB::UO_F32] = ISD::SETNE; in InitCmpLibcallCCs()
538 CCs[RTLIB::UO_F64] = ISD::SETNE; in InitCmpLibcallCCs()
1936 if ((Cond == ISD::SETEQ || Cond == ISD::SETNE) && in SimplifySetCC()
1941 Cond = ISD::SETNE; in SimplifySetCC()
1970 ISD::CondCode CC = Cond == ISD::SETULT ? ISD::SETEQ : ISD::SETNE; in SimplifySetCC()
1979 (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { in SimplifySetCC()
2085 case ISD::SETNE: return DAG.getConstant(1, VT); in SimplifySetCC()
2102 case ISD::SETNE: in SimplifySetCC()
[all …]
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| D | LegalizeIntegerTypes.cpp | 437 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_SADDSUBO()
583 Ofl = DAG.getSetCC(dl, N->getValueType(1), Ofl, Res, ISD::SETNE); in PromoteIntRes_UADDSUBO()
620 DAG.getConstant(0, Hi.getValueType()), ISD::SETNE); in PromoteIntRes_XMULO()
625 Overflow = DAG.getSetCC(DL, N->getValueType(1), SExt, Mul, ISD::SETNE); in PromoteIntRes_XMULO()
768 case ISD::SETNE: in PromoteSetCCOperands()
1638 DAG.getConstant(0, NVT), ISD::SETNE); in ExpandIntRes_CTLZ()
1668 DAG.getConstant(0, NVT), ISD::SETNE); in ExpandIntRes_CTTZ()
1944 ISD::SETEQ : ISD::SETNE); in ExpandIntRes_SADDSUBO()
1947 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); in ExpandIntRes_SADDSUBO()
2195 RHS, DAG.getConstant(0, VT), ISD::SETNE); in ExpandIntRes_XMULO()
[all …]
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| D | LegalizeFloatTypes.cpp | 620 case ISD::SETNE: in SoftenSetCCOperands()
714 CCCode = ISD::SETNE; in SoftenFloatOp_BR_CC()
756 CCCode = ISD::SETNE; in SoftenFloatOp_SELECT_CC()
1326 CCCode = ISD::SETNE; in ExpandFloatOp_BR_CC()
1407 CCCode = ISD::SETNE; in ExpandFloatOp_SELECT_CC()
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| D | LegalizeDAG.cpp | 1961 case ISD::SETONE: CC1 = ISD::SETNE; CC2 = ISD::SETO; Opc = ISD::AND; break; in LegalizeSetCCCondCode()
1967 case ISD::SETUNE: CC1 = ISD::SETNE; CC2 = ISD::SETUO; Opc = ISD::OR; break; in LegalizeSetCCCondCode()
2536 And2, DAG.getConstant(UINT64_C(0), MVT::i64), ISD::SETNE); in ExpandLegalINT_TO_FP()
3506 ISD::SETEQ : ISD::SETNE); in ExpandNode()
3509 SDValue SumSignNE = DAG.getSetCC(dl, OType, LHSSign, SumSign, ISD::SETNE); in ExpandNode()
3597 ISD::SETNE); in ExpandNode()
3600 DAG.getConstant(0, VT), ISD::SETNE); in ExpandNode()
3627 Tmp2, Tmp3, ISD::SETNE); in ExpandNode()
3678 DAG.getCondCode(ISD::SETNE), Tmp3, in ExpandNode()
3716 CC = DAG.getCondCode(ISD::SETNE); in ExpandNode()
[all …]
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| D | SelectionDAG.cpp | 246 case ISD::SETNE: return 0; in isSignedOp()
277 Op = ISD::SETNE; in getSetCCOrOperation()
1491 case ISD::SETNE: return getConstant(C1 != C2, VT); in FoldSetCC()
1516 case ISD::SETNE: if (R==APFloat::cmpUnordered) in FoldSetCC()
6014 case ISD::SETNE: return "setne"; in getOperationName()
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| D | SelectionDAGBuilder.cpp | 1423 if (Cases[0].CC == ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB) in ShouldEmitAsBranches()
1745 ISD::SETNE); in visitBitTestCase()
1757 ISD::SETNE); in visitBitTestCase()
5243 ISD::SETNE); in visitMemCmpCall()
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| D | DAGCombiner.cpp | 2801 (Op1 == ISD::SETNE || Op1 == ISD::SETLT)) { in visitOR()
2810 (Op1 == ISD::SETNE || Op1 == ISD::SETGT)) { in visitOR()
5759 ISD::SETNE); in visitBRCOND()
5825 Equal ? ISD::SETEQ : ISD::SETNE); in visitBRCOND()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelDAGToDAG.cpp | 453 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
494 if (CC == ISD::SETEQ || CC == ISD::SETNE) { in SelectCC()
555 case ISD::SETNE: return PPC::PRED_NE; in getPredicateForSetCC()
595 case ISD::SETNE: Invert = true; return 2; // !Bit #2 = SETUNE in getCRIdxForSetCC()
629 case ISD::SETNE: { in SelectSETCC()
662 case ISD::SETNE: { in SelectSETCC()
1014 N2C->getZExtValue() == 1ULL && CC == ISD::SETNE && in Select()
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| D | PPCISelLowering.cpp | 1257 if (LHSVT.isInteger() && (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
1289 DAG.getConstant(0, MVT::i32), ISD::SETNE); in LowerVAARG()
3556 if (CC == ISD::SETEQ || CC == ISD::SETNE) return Op; in LowerSELECT_CC()
5376 isa<ConstantSDNode>(RHS) && (CC == ISD::SETEQ || CC == ISD::SETNE) && in PerformDAGCombine()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 727 SETNE, // 1 X 1 1 0 True if not equal enumerator
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 206 setCmpLibcallCC(RTLIB::OEQ_F32, ISD::SETNE); in ARMTargetLowering()
207 setCmpLibcallCC(RTLIB::UNE_F32, ISD::SETNE); in ARMTargetLowering()
208 setCmpLibcallCC(RTLIB::OLT_F32, ISD::SETNE); in ARMTargetLowering()
209 setCmpLibcallCC(RTLIB::OLE_F32, ISD::SETNE); in ARMTargetLowering()
210 setCmpLibcallCC(RTLIB::OGE_F32, ISD::SETNE); in ARMTargetLowering()
211 setCmpLibcallCC(RTLIB::OGT_F32, ISD::SETNE); in ARMTargetLowering()
212 setCmpLibcallCC(RTLIB::UO_F32, ISD::SETNE); in ARMTargetLowering()
225 setCmpLibcallCC(RTLIB::OEQ_F64, ISD::SETNE); in ARMTargetLowering()
226 setCmpLibcallCC(RTLIB::UNE_F64, ISD::SETNE); in ARMTargetLowering()
227 setCmpLibcallCC(RTLIB::OLT_F64, ISD::SETNE); in ARMTargetLowering()
[all …]
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrCMovSetCC.td | 93 defm SETNE : SETCC<0x95, "setne", X86_COND_NE>; // not equal to
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| D | X86ISelLowering.cpp | 2935 case ISD::SETNE: return X86::COND_NE; in TranslateX86CC()
2985 case ISD::SETNE: return X86::COND_NE; in TranslateX86CC()
7529 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
7540 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
7546 bool Invert = (CC == ISD::SETNE) ^ in LowerSETCC()
7597 case ISD::SETNE: SSECC = 4; break; in LowerVSETCC()
7643 case ISD::SETNE: Invert = true; in LowerVSETCC()
7799 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, DL, DAG); in LowerSELECT()
7991 SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG); in LowerBRCOND()
8252 CC = ISD::SETNE; in LowerINTRINSIC_WO_CHAIN()
[all …]
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| /external/llvm/lib/Target/PTX/ |
| D | PTXISelLowering.cpp | 158 (CC == ISD::SETEQ || CC == ISD::SETNE)) { in LowerSETCC()
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| D | PTXInstrInfo.td | 709 defm SETPNEu16 : PTX_SETP_I<RegI16, "u16", i16imm, SETNE, "ne">;
722 defm SETPNEu32 : PTX_SETP_I<RegI32, "u32", i32imm, SETNE, "ne">;
735 defm SETPNEu64 : PTX_SETP_I<RegI64, "u64", i64imm, SETNE, "ne">;
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| /external/llvm/lib/Target/Alpha/ |
| D | AlphaISelDAGToDAG.cpp | 322 case ISD::SETNE: case ISD::SETONE: case ISD::SETUNE: in Select()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 649 case ISD::SETNE: return SPCC::ICC_NE; in IntCondCCodeToICC()
668 case ISD::SETNE: in FPCondCCodeToFCC()
864 CC == ISD::SETNE && in LookThroughSetCC()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrFPU.td | 143 def : Pat<(setcc (f32 GPR:$L), (f32 GPR:$R), SETNE),
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| D | MBlazeInstrInfo.td | 755 def : Pat<(setcc (i32 GPR:$L), (i32 GPR:$R), SETNE),
792 (i32 GPR:$T), (i32 GPR:$F), SETNE),
830 def : Pat<(brcond (setcc (i32 GPR:$L), (i32 GPR:$R), SETNE), bb:$T),
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 478 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
788 (setcc node:$lhs, node:$rhs, SETNE)>;
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| /external/llvm/lib/Target/SystemZ/ |
| D | SystemZISelLowering.cpp | 625 case ISD::SETNE: in EmitCmp()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 682 case ISD::SETNE: in EmitCMP()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 424 case ISD::SETNE: in FPCondCCodeToFCC()
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| /external/llvm/lib/Target/CellSPU/ |
| D | SPUISelLowering.cpp | 2601 compareOp = ISD::SETNE; break; in LowerSETCC()
|