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Searched defs:VReg (Results 1 – 17 of 17) sorted by relevance

/external/llvm/lib/CodeGen/
DLiveIntervalUnion.h122 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): in Query()
138 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { in init()
DLiveIntervalUnion.cpp152 LiveInterval *VReg = LiveUnionI.value(); in collectInterferingVRegs() local
DLiveRangeEdit.cpp35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom() local
DMachineFunction.cpp398 unsigned VReg = MRI.getLiveInVirtReg(PReg); in addLiveIn() local
DTailDuplication.cpp222 unsigned VReg = SSAUpdateVRs[i]; in TailDuplicateAndUpdate() local
DTwoAddressInstructionPass.cpp1622 unsigned VReg = TargetRegisterInfo::index2VirtReg(i); in runOnMachineFunction() local
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp251 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); in getVR() local
282 unsigned VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local
402 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg()
456 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); in EmitSubregNode() local
547 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); in EmitCopyToRegClassNode() local
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp1831 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); in LowerFormalArguments_SVR4() local
1850 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); in LowerFormalArguments_SVR4() local
2016 unsigned VReg; in LowerFormalArguments_Darwin() local
2039 unsigned VReg; in LowerFormalArguments_Darwin() local
2066 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); in LowerFormalArguments_Darwin() local
2080 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_Darwin() local
2115 unsigned VReg; in LowerFormalArguments_Darwin() local
2138 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); in LowerFormalArguments_Darwin() local
2213 unsigned VReg; in LowerFormalArguments_Darwin() local
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp841 unsigned VReg = in LowerFormalArguments() local
846 unsigned VReg = in LowerFormalArguments() local
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp636 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); in LowerLOAD() local
831 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); in LowerSTORE() local
1185 unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass); in LowerFormalArguments() local
1233 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::VECREGRegClass); in LowerFormalArguments() local
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp211 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments() local
323 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments() local
/external/llvm/lib/Target/ARM/
DThumb1RegisterInfo.cpp598 unsigned VReg = 0; in eliminateFrameIndex() local
DARMISelLowering.cpp2550 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); in VarArgStyleRegisters() local
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1124 unsigned VReg = RegInfo.createVirtualRegister( in LowerCCCArguments() local
1175 unsigned VReg = RegInfo.createVirtualRegister( in LowerCCCArguments() local
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp333 unsigned VReg = in LowerCCCArguments() local
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp766 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); in AddLiveIn() local
2706 unsigned VReg = AddLiveIn(MF, *Reg, Mips::CPU64RegsRegisterClass); in CopyMips64ByValRegs() local
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp2007 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], in LowerFormalArguments() local
2034 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], in LowerFormalArguments() local