/external/llvm/lib/CodeGen/ |
D | LiveIntervalUnion.h | 122 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): in Query() 138 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { in init()
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D | LiveIntervalUnion.cpp | 152 LiveInterval *VReg = LiveUnionI.value(); in collectInterferingVRegs() local
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D | LiveRangeEdit.cpp | 35 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); in createFrom() local
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D | MachineFunction.cpp | 398 unsigned VReg = MRI.getLiveInVirtReg(PReg); in addLiveIn() local
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D | TailDuplication.cpp | 222 unsigned VReg = SSAUpdateVRs[i]; in TailDuplicateAndUpdate() local
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D | TwoAddressInstructionPass.cpp | 1622 unsigned VReg = TargetRegisterInfo::index2VirtReg(i); in runOnMachineFunction() local
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | InstrEmitter.cpp | 251 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); in getVR() local 282 unsigned VReg = getVR(Op, VRBaseMap); in AddRegisterOperand() local 402 unsigned InstrEmitter::ConstrainForSubReg(unsigned VReg, unsigned SubIdx, in ConstrainForSubReg() 456 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); in EmitSubregNode() local 547 unsigned VReg = getVR(Node->getOperand(0), VRBaseMap); in EmitCopyToRegClassNode() local
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/external/llvm/lib/Target/PowerPC/ |
D | PPCISelLowering.cpp | 1831 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); in LowerFormalArguments_SVR4() local 1850 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); in LowerFormalArguments_SVR4() local 2016 unsigned VReg; in LowerFormalArguments_Darwin() local 2039 unsigned VReg; in LowerFormalArguments_Darwin() local 2066 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); in LowerFormalArguments_Darwin() local 2080 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_Darwin() local 2115 unsigned VReg; in LowerFormalArguments_Darwin() local 2138 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); in LowerFormalArguments_Darwin() local 2213 unsigned VReg; in LowerFormalArguments_Darwin() local
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonISelLowering.cpp | 841 unsigned VReg = in LowerFormalArguments() local 846 unsigned VReg = in LowerFormalArguments() local
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/external/llvm/lib/Target/CellSPU/ |
D | SPUISelLowering.cpp | 636 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); in LowerLOAD() local 831 unsigned VReg = RegInfo.createVirtualRegister(&SPU::R32CRegClass); in LowerSTORE() local 1185 unsigned VReg = RegInfo.createVirtualRegister(ArgRegClass); in LowerFormalArguments() local 1233 unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::VECREGRegClass); in LowerFormalArguments() local
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/external/llvm/lib/Target/Sparc/ |
D | SparcISelLowering.cpp | 211 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments() local 323 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); in LowerFormalArguments() local
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/external/llvm/lib/Target/ARM/ |
D | Thumb1RegisterInfo.cpp | 598 unsigned VReg = 0; in eliminateFrameIndex() local
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D | ARMISelLowering.cpp | 2550 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); in VarArgStyleRegisters() local
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/external/llvm/lib/Target/XCore/ |
D | XCoreISelLowering.cpp | 1124 unsigned VReg = RegInfo.createVirtualRegister( in LowerCCCArguments() local 1175 unsigned VReg = RegInfo.createVirtualRegister( in LowerCCCArguments() local
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/external/llvm/lib/Target/MSP430/ |
D | MSP430ISelLowering.cpp | 333 unsigned VReg = in LowerCCCArguments() local
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/external/llvm/lib/Target/Mips/ |
D | MipsISelLowering.cpp | 766 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); in AddLiveIn() local 2706 unsigned VReg = AddLiveIn(MF, *Reg, Mips::CPU64RegsRegisterClass); in CopyMips64ByValRegs() local
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/external/llvm/lib/Target/X86/ |
D | X86ISelLowering.cpp | 2007 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], in LowerFormalArguments() local 2034 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], in LowerFormalArguments() local
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