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Searched refs:FPSCR (Results 1 – 19 of 19) sorted by relevance

/external/valgrind/main/none/tests/arm/
Dvfp.stdout.exp726 vcmp.f64 d0, d19 :: FPSCR 0x80000000 Dd 0xc00ba752 5460aa65 Dm 0xc004fef9 db22d0e5
727 vcmp.f64 d11, d16 :: FPSCR 0x20000000 Dd 0x40d6ecdc cccccccd Dm 0x40aac300 00000000
728 vcmp.f64 d21, d30 :: FPSCR 0x20000000 Dd 0xc0b1ac80 00000000 Dm 0xc11b9be6 00000000
729 vcmp.f64 d7, d28 :: FPSCR 0x20000000 Dd 0x407a9800 00000000 Dm 0xc07c84cc cccccccd
730 vcmp.f64 d29, d3 :: FPSCR 0x20000000 Dd 0x7ff00000 00000000 Dm 0x40e0e04e 66666666
731 vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x40000000 00000000 Dm 0x40000000 00000000
732 vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x40280bc6 a7ef9db2 Dm 0x40280bc6 a7ef9db2
733 vcmp.f64 d3, d22 :: FPSCR 0x60000000 Dd 0x00000000 00000000 Dm 0x00000000 00000000
734 vcmp.f64 d9, d2 :: FPSCR 0x60000000 Dd 0x7ff00000 00000000 Dm 0x7ff00000 00000000
735 vcmp.f64 d30, d15 :: FPSCR 0x60000000 Dd 0xfff00000 00000000 Dm 0xfff00000 00000000
[all …]
/external/llvm/lib/Target/ARM/
DARMRegisterInfo.td156 // We model fpscr with two registers: FPSCR models the control bits and will be
161 def FPSCR : ARMReg<3, "fpscr">;
163 let Aliases = [FPSCR];
DARMInstrVFP.td778 // And the Z bit '0' variants, i.e. use the rounding mode specified by FPSCR.
779 let Uses = [FPSCR] in {
1253 // APSR is the application level alias of CPSR. This FPSCR N, Z, C, V flags
1259 // Application level FPSCR -> GPR
1260 let hasSideEffects = 1, Uses = [FPSCR] in
1266 let Uses = [FPSCR] in {
1298 let Defs = [FPSCR] in {
1299 // Application level GPR -> FPSCR
DARMBaseRegisterInfo.cpp81 Reserved.set(ARM::FPSCR); in getReservedRegs()
DARMISelLowering.cpp3459 SDValue FPSCR = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, MVT::i32, in LowerFLT_ROUNDS_() local
3462 SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR, in LowerFLT_ROUNDS_()
/external/valgrind/main/VEX/priv/
Dhost_arm_defs.c1332 i->ARMin.FPSCR.toFPSCR = toFPSCR; in ARMInstr_FPSCR()
1333 i->ARMin.FPSCR.iReg = iReg; in ARMInstr_FPSCR()
1754 if (i->ARMin.FPSCR.toFPSCR) { in ppARMInstr()
1756 ppHRegARM(i->ARMin.FPSCR.iReg); in ppARMInstr()
1759 ppHRegARM(i->ARMin.FPSCR.iReg); in ppARMInstr()
2101 if (i->ARMin.FPSCR.toFPSCR) in getRegUsage_ARMInstr()
2102 addHRegUse(u, HRmRead, i->ARMin.FPSCR.iReg); in getRegUsage_ARMInstr()
2104 addHRegUse(u, HRmWrite, i->ARMin.FPSCR.iReg); in getRegUsage_ARMInstr()
2284 i->ARMin.FPSCR.iReg = lookupHRegRemap(m, i->ARMin.FPSCR.iReg); in mapRegs_ARMInstr()
3288 Bool toFPSCR = i->ARMin.FPSCR.toFPSCR; in emit_ARMInstr()
[all …]
Dhost_arm_defs.h818 } FPSCR; member
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.td69 // bits in the FPSCR which is not modelled.
1121 // Instructions to manipulate FPSCR. Only long double handling uses these.
1122 // FPSCR is not modelled; we use the SDNode Flag to keep things in order.
1135 // instruction had no outputs (because we aren't modelling the FPSCR) and
/external/oprofile/events/ppc64/power6/
Devents754 … minimum:1000 name:PM_FPU0_FPSCR_GRP122 : (Group 122 pm_fpu0_misc2) FPU0 executed FPSCR instruction
778 … minimum:1000 name:PM_FPU1_FPSCR_GRP126 : (Group 126 pm_fpu1_misc2) FPU1 executed FPSCR instruction
796 …zero minimum:1000 name:PM_FPU_FPSCR_GRP129 : (Group 129 pm_fpu_misc) FPU executed FPSCR instruction
/external/valgrind/main/memcheck/
Dmc_machine.c872 if (o == GOF(FPSCR) && sz == 4) return -1; in get_otrack_shadow_offset_wrk()
/external/oprofile/events/ppc64/970/
Devents155 … um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP14 : (Group 14 pm_fpu7) FPU0 executed FPSCR instruction
/external/oprofile/events/ppc64/970MP/
Devents160 … um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP14 : (Group 14 pm_fpu7) FPU0 executed FPSCR instruction
/external/oprofile/events/ppc64/power5++/
Devents557 … um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP89 : (Group 89 pm_fpu8) FPU0 executed FPSCR instruction
863 …:zero minimum:1000 name:PM_FPU0_FPSCR_GRP140 : (Group 140 pm_fpuX1) FPU0 executed FPSCR instruction
/external/oprofile/events/ppc64/power5/
Devents704 … um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP86 : (Group 86 pm_fpu8) FPU0 executed FPSCR instruction
1096 …:zero minimum:1000 name:PM_FPU0_FPSCR_GRP135 : (Group 135 pm_fpuX1) FPU0 executed FPSCR instruction
/external/oprofile/events/ppc64/power5+/
Devents728 … um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP89 : (Group 89 pm_fpu8) FPU0 executed FPSCR instruction
1136 …:zero minimum:1000 name:PM_FPU0_FPSCR_GRP140 : (Group 140 pm_fpuX1) FPU0 executed FPSCR instruction
/external/oprofile/events/ppc64/power4/
Devents345 … um:zero minimum:1000 name:PM_FPU0_FPSCR_GRP33 : (Group 33 pm_fpu7) FPU0 executed FPSCR instruction
/external/v8/
DChangeLog1556 Avoided trashing the FPSCR when calculating Math.floor on ARM.
/external/oprofile/events/ppc64/power7/
Devents1104 …inimum:1000 name:PM_VSU0_FPSCR_GRP136 : (Group 136 pm_vsu15) Move to/from FPSCR type instruction i…
/external/webkit/Source/JavaScriptCore/
DChangeLog-2011-02-1615685 looks quicker than testing FPSCR for exception.