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Searched refs:MI (Results 1 – 25 of 344) sorted by relevance

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/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp29 void llvm::EmitAnyX86InstComments(const MCInst *MI, raw_ostream &OS, in EmitAnyX86InstComments() argument
35 switch (MI->getOpcode()) { in EmitAnyX86InstComments()
37 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
38 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
39 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); in EmitAnyX86InstComments()
42 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
43 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
44 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
45 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); in EmitAnyX86InstComments()
49 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
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DX86ATTInstPrinter.h30 virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
34 bool printAliasInstr(const MCInst *MI, raw_ostream &OS);
37 void printInstruction(const MCInst *MI, raw_ostream &OS);
40 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
41 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &OS);
42 void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &OS);
43 void print_pcrel_imm(const MCInst *MI, unsigned OpNo, raw_ostream &OS);
45 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printopaquemem() argument
46 printMemReference(MI, OpNo, O); in printopaquemem()
49 void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printi8mem() argument
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DX86IntelInstPrinter.h31 virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
34 void printInstruction(const MCInst *MI, raw_ostream &O);
37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
38 void printMemReference(const MCInst *MI, unsigned Op, raw_ostream &O);
39 void printSSECC(const MCInst *MI, unsigned Op, raw_ostream &O);
40 void print_pcrel_imm(const MCInst *MI, unsigned OpNo, raw_ostream &O);
42 void printopaquemem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printopaquemem() argument
44 printMemReference(MI, OpNo, O); in printopaquemem()
47 void printi8mem(const MCInst *MI, unsigned OpNo, raw_ostream &O) { in printi8mem() argument
49 printMemReference(MI, OpNo, O); in printi8mem()
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/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.h29 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
33 void printInstruction(const MCInst *MI, raw_ostream &O);
37 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
39 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
40 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
42 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
43 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
44 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
45 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
46 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
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DARMInstPrinter.cpp51 void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
53 unsigned Opcode = MI->getOpcode(); in printInst()
58 const MCOperand &Dst = MI->getOperand(0); in printInst()
59 const MCOperand &MO1 = MI->getOperand(1); in printInst()
60 const MCOperand &MO2 = MI->getOperand(2); in printInst()
61 const MCOperand &MO3 = MI->getOperand(3); in printInst()
64 printSBitModifierOperand(MI, 6, O); in printInst()
65 printPredicateOperand(MI, 4, O); in printInst()
78 const MCOperand &Dst = MI->getOperand(0); in printInst()
79 const MCOperand &MO1 = MI->getOperand(1); in printInst()
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/external/llvm/lib/Target/ARM/
DARMCodeEmitter.cpp77 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
85 void emitInstruction(const MachineInstr &MI);
92 void emitConstPoolInstruction(const MachineInstr &MI);
93 void emitMOVi32immInstruction(const MachineInstr &MI);
94 void emitMOVi2piecesInstruction(const MachineInstr &MI);
95 void emitLEApcrelInstruction(const MachineInstr &MI);
96 void emitLEApcrelJTInstruction(const MachineInstr &MI);
97 void emitPseudoMoveInstruction(const MachineInstr &MI);
99 void emitPseudoInstruction(const MachineInstr &MI);
100 unsigned getMachineSoRegOpValue(const MachineInstr &MI,
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DThumb2SizeReduction.cpp152 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry,
156 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI,
159 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI,
165 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI,
172 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI,
252 Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry, in VerifyPredAndCC() argument
282 if (!HasImplicitCPSRDef(MI->getDesc())) in VerifyPredAndCC()
294 static bool VerifyLowRegs(MachineInstr *MI) { in VerifyLowRegs() argument
295 unsigned Opc = MI->getOpcode(); in VerifyLowRegs()
301 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in VerifyLowRegs()
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DMLxExpansionPass.cpp60 void pushStack(MachineInstr *MI);
61 MachineInstr *getAccDefMI(MachineInstr *MI) const;
62 unsigned getDefReg(MachineInstr *MI) const;
63 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
64 bool FindMLxHazard(MachineInstr *MI);
65 void ExpandFPMLxInstruction(MachineBasicBlock &MBB, MachineInstr *MI,
78 void MLxExpansion::pushStack(MachineInstr *MI) { in pushStack() argument
79 LastMIs[MIIdx] = MI; in pushStack()
84 MachineInstr *MLxExpansion::getAccDefMI(MachineInstr *MI) const { in getAccDefMI()
87 unsigned Reg = MI->getOperand(1).getReg(); in getAccDefMI()
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DARMExpandPseudoInsts.cpp375 MachineInstr &MI = *MBBI; in ExpandVLD() local
376 MachineBasicBlock &MBB = *MI.getParent(); in ExpandVLD()
378 const NEONLdStTableEntry *TableEntry = LookupNEONLdSt(MI.getOpcode()); in ExpandVLD()
383 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, MI.getDebugLoc(), in ExpandVLD()
387 bool DstIsDead = MI.getOperand(OpIdx).isDead(); in ExpandVLD()
388 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD()
400 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
403 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
404 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
407 MIB.addOperand(MI.getOperand(OpIdx++)); in ExpandVLD()
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/external/llvm/lib/CodeGen/
DExpandPostRAPseudos.cpp50 bool LowerSubregToReg(MachineInstr *MI);
51 bool LowerCopy(MachineInstr *MI);
53 void TransferDeadFlag(MachineInstr *MI, unsigned DstReg,
55 void TransferImplicitDefs(MachineInstr *MI);
69 ExpandPostRA::TransferDeadFlag(MachineInstr *MI, unsigned DstReg, in TransferDeadFlag() argument
72 prior(MachineBasicBlock::iterator(MI)); ; --MII) { in TransferDeadFlag()
75 assert(MII != MI->getParent()->begin() && in TransferDeadFlag()
84 ExpandPostRA::TransferImplicitDefs(MachineInstr *MI) { in TransferImplicitDefs() argument
85 MachineBasicBlock::iterator CopyMI = MI; in TransferImplicitDefs()
88 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { in TransferImplicitDefs()
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DTargetInstrInfoImpl.cpp61 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI, in commuteInstruction() argument
63 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction()
65 if (HasDef && !MI->getOperand(0).isReg()) in commuteInstruction()
69 if (!findCommutedOpIndices(MI, Idx1, Idx2)) { in commuteInstruction()
72 Msg << "Don't know how to commute: " << *MI; in commuteInstruction()
76 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() && in commuteInstruction()
78 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0; in commuteInstruction()
79 unsigned Reg1 = MI->getOperand(Idx1).getReg(); in commuteInstruction()
80 unsigned Reg2 = MI->getOperand(Idx2).getReg(); in commuteInstruction()
81 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0; in commuteInstruction()
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DMachineLICM.cpp153 MachineInstr *MI; member
157 : MI(mi), Def(def), FI(fi) {} in CandidateInfo()
167 void HoistPostRA(MachineInstr *MI, unsigned Def);
171 void ProcessMI(MachineInstr *MI,
195 bool HasLoopPHIUse(const MachineInstr *MI) const;
200 bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
203 bool IsCheapInstruction(MachineInstr &MI) const;
213 void UpdateBackTraceRegPressure(const MachineInstr *MI);
217 bool IsProfitableToHoist(MachineInstr &MI);
246 void getRegisterClassIDAndCost(const MachineInstr *MI,
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/external/llvm/lib/Target/PowerPC/InstPrinter/
DPPCInstPrinter.cpp30 void PPCInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
33 if (MI->getOpcode() == PPC::RLWINM) { in printInst()
34 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
35 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
36 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
46 printOperand(MI, 0, O); in printInst()
48 printOperand(MI, 1, O); in printInst()
56 if ((MI->getOpcode() == PPC::OR || MI->getOpcode() == PPC::OR8) && in printInst()
57 MI->getOperand(1).getReg() == MI->getOperand(2).getReg()) { in printInst()
59 printOperand(MI, 0, O); in printInst()
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/external/llvm/lib/Target/Mips/
DMipsCodeEmitter.cpp83 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
85 void emitInstruction(const MachineInstr &MI);
102 unsigned getMachineOpValue(const MachineInstr &MI,
105 unsigned getRelocation(const MachineInstr &MI,
108 unsigned getJumpTargetOpValue(const MachineInstr &MI, unsigned OpNo) const;
110 unsigned getBranchTargetOpValue(const MachineInstr &MI,
112 unsigned getMemEncoding(const MachineInstr &MI, unsigned OpNo) const;
113 unsigned getSizeExtEncoding(const MachineInstr &MI, unsigned OpNo) const;
114 unsigned getSizeInsEncoding(const MachineInstr &MI, unsigned OpNo) const;
116 int emitULW(const MachineInstr &MI);
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/external/llvm/lib/Target/CellSPU/
DSPUAsmPrinter.cpp51 void printInstruction(const MachineInstr *MI, raw_ostream &OS);
55 void EmitInstruction(const MachineInstr *MI) { in EmitInstruction() argument
58 printInstruction(MI, OS); in EmitInstruction()
63 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) { in printOperand() argument
64 const MachineOperand &MO = MI->getOperand(OpNo); in printOperand()
74 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
77 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
83 printU7ImmOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) in printU7ImmOperand() argument
85 unsigned int value = MI->getOperand(OpNo).getImm(); in printU7ImmOperand()
91 printShufAddr(const MachineInstr *MI, unsigned OpNo, raw_ostream &O) in printShufAddr() argument
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/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp67 uint64_t getBinaryCodeForInstr(const MCInst &MI,
72 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
78 uint32_t getHiLo16ImmOpValue(const MCInst &MI, unsigned OpIdx,
81 bool EncodeAddrModeOpValues(const MCInst &MI, unsigned OpIdx,
87 uint32_t getThumbBLTargetOpValue(const MCInst &MI, unsigned OpIdx,
92 uint32_t getThumbBLXTargetOpValue(const MCInst &MI, unsigned OpIdx,
96 uint32_t getThumbBRTargetOpValue(const MCInst &MI, unsigned OpIdx,
100 uint32_t getThumbBCCTargetOpValue(const MCInst &MI, unsigned OpIdx,
104 uint32_t getThumbCBTargetOpValue(const MCInst &MI, unsigned OpIdx,
109 uint32_t getBranchTargetOpValue(const MCInst &MI, unsigned OpIdx,
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/external/llvm/lib/Target/Hexagon/
DHexagonRegisterInfo.cpp121 MachineInstr &MI = *I; in eliminateCallFramePseudoInstr() local
123 if (MI.getOpcode() == Hexagon::ADJCALLSTACKDOWN) { in eliminateCallFramePseudoInstr()
125 } else if (MI.getOpcode() == Hexagon::ADJCALLSTACKUP) { in eliminateCallFramePseudoInstr()
142 MachineInstr &MI = *II; in eliminateFrameIndex() local
143 while (!MI.getOperand(i).isFI()) { in eliminateFrameIndex()
145 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); in eliminateFrameIndex()
148 int FrameIndex = MI.getOperand(i).getIndex(); in eliminateFrameIndex()
151 MachineFunction &MF = *MI.getParent()->getParent(); in eliminateFrameIndex()
165 TII.isValidOffset(MI.getOpcode(), (FrameSize+Offset)) && in eliminateFrameIndex()
166 !TII.isSpillPredRegOp(&MI)) { in eliminateFrameIndex()
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DHexagonAsmPrinter.h39 virtual void EmitInstruction(const MachineInstr *MI);
43 void printOperand(const MachineInstr *MI, unsigned OpNo, raw_ostream &O);
44 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
47 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
55 void printInstruction(const MachineInstr *MI, raw_ostream &O);
69 void printImmOperand(const MachineInstr *MI, unsigned OpNo, in printImmOperand() argument
71 int value = MI->getOperand(OpNo).getImm(); in printImmOperand()
75 void printNegImmOperand(const MachineInstr *MI, unsigned OpNo, in printNegImmOperand() argument
77 int value = MI->getOperand(OpNo).getImm(); in printNegImmOperand()
81 void printMEMriOperand(const MachineInstr *MI, unsigned OpNo, in printMEMriOperand() argument
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/external/llvm/lib/Target/Hexagon/InstPrinter/
DHexagonInstPrinter.cpp38 void HexagonInstPrinter::printInst(const MCInst *MI, raw_ostream &O, in printInst() argument
44 if (MI->getOpcode() == Hexagon::ENDLOOP0) { in printInst()
53 printInstruction(MI, O); in printInst()
57 void HexagonInstPrinter::printOperand(const MCInst *MI, unsigned OpNo, in printOperand() argument
59 const MCOperand& MO = MI->getOperand(OpNo); in printOperand()
66 printImmOperand(MI, OpNo, O); in printOperand()
73 (const MCInst *MI, unsigned OpNo, raw_ostream &O) const { in printImmOperand() argument
74 O << MI->getOperand(OpNo).getImm(); in printImmOperand()
77 void HexagonInstPrinter::printExtOperand(const MCInst *MI, unsigned OpNo, in printExtOperand() argument
79 O << MI->getOperand(OpNo).getImm(); in printExtOperand()
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DHexagonInstPrinter.h27 virtual void printInst(const MCInst *MI, raw_ostream &O, StringRef Annot);
29 void printInstruction(const MCInst *MI, raw_ostream &O);
33 void printOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;
34 void printImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;
35 void printExtOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O) const;
36 void printUnsignedImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
38 void printNegImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
40 void printNOneImmOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
42 void printMEMriOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
44 void printFrameIndexOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O)
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/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp38 unsigned getDirectBrEncoding(const MCInst &MI, unsigned OpNo,
40 unsigned getCondBrEncoding(const MCInst &MI, unsigned OpNo,
42 unsigned getHA16Encoding(const MCInst &MI, unsigned OpNo,
44 unsigned getLO16Encoding(const MCInst &MI, unsigned OpNo,
46 unsigned getMemRIEncoding(const MCInst &MI, unsigned OpNo,
48 unsigned getMemRIXEncoding(const MCInst &MI, unsigned OpNo,
50 unsigned get_crbitm_encoding(const MCInst &MI, unsigned OpNo,
55 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
60 uint64_t getBinaryCodeForInstr(const MCInst &MI,
62 void EncodeInstruction(const MCInst &MI, raw_ostream &OS, in EncodeInstruction() argument
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/external/llvm/lib/Target/PowerPC/
DPPCCodeEmitter.cpp53 uint64_t getBinaryCodeForInstr(const MachineInstr &MI) const;
60 unsigned getMachineOpValue(const MachineInstr &MI,
63 unsigned get_crbitm_encoding(const MachineInstr &MI, unsigned OpNo) const;
64 unsigned getDirectBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
65 unsigned getCondBrEncoding(const MachineInstr &MI, unsigned OpNo) const;
67 unsigned getHA16Encoding(const MachineInstr &MI, unsigned OpNo) const;
68 unsigned getLO16Encoding(const MachineInstr &MI, unsigned OpNo) const;
69 unsigned getMemRIEncoding(const MachineInstr &MI, unsigned OpNo) const;
70 unsigned getMemRIXEncoding(const MachineInstr &MI, unsigned OpNo) const;
114 const MachineInstr &MI = *I; in emitBasicBlock() local
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/external/llvm/lib/Target/Sparc/
DSparcAsmPrinter.cpp40 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
41 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &OS,
43 void printCCOperand(const MachineInstr *MI, int opNum, raw_ostream &OS);
45 virtual void EmitInstruction(const MachineInstr *MI) { in EmitInstruction() argument
48 printInstruction(MI, OS); in EmitInstruction()
51 void printInstruction(const MachineInstr *MI, raw_ostream &OS);// autogen'd.
54 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
57 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo,
61 bool printGetPCX(const MachineInstr *MI, unsigned OpNo, raw_ostream &OS);
66 virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
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/external/llvm/lib/Target/XCore/
DXCoreAsmPrinter.cpp55 void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
64 void printMemOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
65 void printInlineJT(const MachineInstr *MI, int opNum, raw_ostream &O,
67 void printInlineJT32(const MachineInstr *MI, int opNum, raw_ostream &O) { in printInlineJT32() argument
68 printInlineJT(MI, opNum, O, ".jmptable32"); in printInlineJT32()
70 void printOperand(const MachineInstr *MI, int opNum, raw_ostream &O);
71 bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
78 void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd.
82 void EmitInstruction(const MachineInstr *MI);
84 virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
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/external/llvm/include/llvm/Target/
DTargetInstrInfo.h65 bool isTriviallyReMaterializable(const MachineInstr *MI,
67 return MI->getOpcode() == TargetOpcode::IMPLICIT_DEF ||
68 (MI->getDesc().isRematerializable() &&
69 (isReallyTriviallyReMaterializable(MI, AA) ||
70 isReallyTriviallyReMaterializableGeneric(MI, AA)));
80 virtual bool isReallyTriviallyReMaterializable(const MachineInstr *MI, in isReallyTriviallyReMaterializable() argument
91 bool isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
110 virtual bool isCoalescableExtInstr(const MachineInstr &MI, in isCoalescableExtInstr() argument
121 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI, in isLoadFromStackSlot() argument
129 virtual unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI, in isLoadFromStackSlotPostFE() argument
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