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Searched refs:OpNum (Results 1 – 24 of 24) sorted by relevance

/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.h39 void printSORegRegOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
40 void printSORegImmOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
42 void printAddrModeTBB(const MCInst *MI, unsigned OpNum, raw_ostream &O);
43 void printAddrModeTBH(const MCInst *MI, unsigned OpNum, raw_ostream &O);
44 void printAddrMode2Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
45 void printAM2PostIndexOp(const MCInst *MI, unsigned OpNum, raw_ostream &O);
46 void printAM2PreOrOffsetIndexOp(const MCInst *MI, unsigned OpNum,
48 void printAddrMode2OffsetOperand(const MCInst *MI, unsigned OpNum,
51 void printAddrMode3Operand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
52 void printAddrMode3OffsetOperand(const MCInst *MI, unsigned OpNum,
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DARMInstPrinter.cpp226 void ARMInstPrinter::printT2LdrLabelOperand(const MCInst *MI, unsigned OpNum, in printT2LdrLabelOperand() argument
228 const MCOperand &MO1 = MI->getOperand(OpNum); in printT2LdrLabelOperand()
242 void ARMInstPrinter::printSORegRegOperand(const MCInst *MI, unsigned OpNum, in printSORegRegOperand() argument
244 const MCOperand &MO1 = MI->getOperand(OpNum); in printSORegRegOperand()
245 const MCOperand &MO2 = MI->getOperand(OpNum+1); in printSORegRegOperand()
246 const MCOperand &MO3 = MI->getOperand(OpNum+2); in printSORegRegOperand()
260 void ARMInstPrinter::printSORegImmOperand(const MCInst *MI, unsigned OpNum, in printSORegImmOperand() argument
262 const MCOperand &MO1 = MI->getOperand(OpNum); in printSORegImmOperand()
263 const MCOperand &MO2 = MI->getOperand(OpNum+1); in printSORegImmOperand()
369 unsigned OpNum, in printAddrMode2OffsetOperand() argument
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/external/llvm/lib/Bitcode/Reader/
DBitcodeReader.cpp2018 unsigned OpNum = 0; in ParseFunctionBody() local
2020 if (getValueTypePair(Record, OpNum, NextValueNo, LHS) || in ParseFunctionBody()
2021 getValue(Record, OpNum, LHS->getType(), RHS) || in ParseFunctionBody()
2022 OpNum+1 > Record.size()) in ParseFunctionBody()
2025 int Opc = GetDecodedBinaryOpcode(Record[OpNum++], LHS->getType()); in ParseFunctionBody()
2029 if (OpNum < Record.size()) { in ParseFunctionBody()
2034 if (Record[OpNum] & (1 << bitc::OBO_NO_SIGNED_WRAP)) in ParseFunctionBody()
2036 if (Record[OpNum] & (1 << bitc::OBO_NO_UNSIGNED_WRAP)) in ParseFunctionBody()
2042 if (Record[OpNum] & (1 << bitc::PEO_EXACT)) in ParseFunctionBody()
2049 unsigned OpNum = 0; in ParseFunctionBody() local
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/external/llvm/lib/Target/MSP430/
DMSP430AsmPrinter.cpp49 void printOperand(const MachineInstr *MI, int OpNum,
51 void printSrcMemOperand(const MachineInstr *MI, int OpNum,
64 void MSP430AsmPrinter::printOperand(const MachineInstr *MI, int OpNum, in printOperand() argument
66 const MachineOperand &MO = MI->getOperand(OpNum); in printOperand()
111 void MSP430AsmPrinter::printSrcMemOperand(const MachineInstr *MI, int OpNum, in printSrcMemOperand() argument
113 const MachineOperand &Base = MI->getOperand(OpNum); in printSrcMemOperand()
114 const MachineOperand &Disp = MI->getOperand(OpNum+1); in printSrcMemOperand()
121 printOperand(MI, OpNum+1, O, "nohash"); in printSrcMemOperand()
126 printOperand(MI, OpNum, O); in printSrcMemOperand()
DMSP430InstrInfo.td19 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
20 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
/external/llvm/lib/Target/
DTargetInstrInfo.cpp30 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass() argument
32 if (OpNum >= MCID.getNumOperands()) in getRegClass()
35 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass()
36 if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) in getRegClass()
/external/llvm/lib/Target/ARM/
DARMAsmPrinter.cpp323 void ARMAsmPrinter::printOperand(const MachineInstr *MI, int OpNum, in printOperand() argument
325 const MachineOperand &MO = MI->getOperand(OpNum); in printOperand()
410 bool ARMAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, in PrintAsmOperand() argument
420 if (MI->getOperand(OpNum).isReg()) { in PrintAsmOperand()
422 << ARMInstPrinter::getRegisterName(MI->getOperand(OpNum).getReg()) in PrintAsmOperand()
428 if (!MI->getOperand(OpNum).isImm()) in PrintAsmOperand()
430 O << MI->getOperand(OpNum).getImm(); in PrintAsmOperand()
434 printOperand(MI, OpNum, O); in PrintAsmOperand()
440 if (MI->getOperand(OpNum).isReg()) { in PrintAsmOperand()
441 unsigned Reg = MI->getOperand(OpNum).getReg(); in PrintAsmOperand()
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DARMAsmPrinter.h57 void printOperand(const MachineInstr *MI, int OpNum, raw_ostream &O,
60 virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNum,
63 virtual bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
DThumb2SizeReduction.cpp337 unsigned OpNum = 3; // First 'rest' of operands. in ReduceLoadStore() local
375 OpNum = 4; in ReduceLoadStore()
396 OpNum = 0; in ReduceLoadStore()
405 OpNum = 2; in ReduceLoadStore()
413 OpNum = 0; in ReduceLoadStore()
420 OpNum = 2; in ReduceLoadStore()
470 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum) in ReduceLoadStore()
471 MIB.addOperand(MI->getOperand(OpNum)); in ReduceLoadStore()
DARMLoadStoreOptimizer.cpp785 for (unsigned OpNum = 3, e = MI->getNumOperands(); OpNum != e; ++OpNum) in MergeBaseUpdateLSMultiple() local
786 MIB.addOperand(MI->getOperand(OpNum)); in MergeBaseUpdateLSMultiple()
DARMISelLowering.cpp4409 unsigned OpNum = (PFEntry >> 26) & 0x0F; in GeneratePerfectShuffle() local
4431 if (OpNum == OP_COPY) { in GeneratePerfectShuffle()
4442 switch (OpNum) { in GeneratePerfectShuffle()
4460 OpLHS, DAG.getConstant(OpNum-OP_VDUP0, MVT::i32)); in GeneratePerfectShuffle()
4466 DAG.getConstant(OpNum-OP_VEXT1+1, MVT::i32)); in GeneratePerfectShuffle()
4470 OpLHS, OpRHS).getValue(OpNum-OP_VUZPL); in GeneratePerfectShuffle()
4474 OpLHS, OpRHS).getValue(OpNum-OP_VZIPL); in GeneratePerfectShuffle()
4478 OpLHS, OpRHS).getValue(OpNum-OP_VTRNL); in GeneratePerfectShuffle()
/external/llvm/include/llvm/MC/
DMCInstrDesc.h148 int getOperandConstraint(unsigned OpNum, in getOperandConstraint() argument
150 if (OpNum < NumOperands && in getOperandConstraint()
151 (OpInfo[OpNum].Constraints & (1 << Constraint))) { in getOperandConstraint()
153 return (int)(OpInfo[OpNum].Constraints >> Pos) & 0xf; in getOperandConstraint()
/external/llvm/utils/PerfectShuffle/
DPerfectShuffle.cpp106 unsigned short OpNum; member
112 : ShuffleMask(shufflemask), OpNum(opnum), Name(name), Cost(cost) { in Operator()
394 unsigned OpNum = ShufTab[i].Op ? ShufTab[i].Op->OpNum : 0; in main() local
395 assert(OpNum < 16 && "Too few bits to encode operation!"); in main()
402 unsigned Val = (CostSat << 30) | (OpNum << 26) | (LHS << 13) | RHS; in main()
/external/llvm/lib/Target/ARM/MCTargetDesc/
DARMMCCodeEmitter.cpp262 unsigned getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum,
264 unsigned getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum,
266 unsigned getT2AddrModeImm8OffsetOpValue(const MCInst &MI, unsigned OpNum,
268 unsigned getT2AddrModeImm12OffsetOpValue(const MCInst &MI, unsigned OpNum,
1202 getT2AddrModeSORegOpValue(const MCInst &MI, unsigned OpNum, in getT2AddrModeSORegOpValue() argument
1204 const MCOperand &MO1 = MI.getOperand(OpNum); in getT2AddrModeSORegOpValue()
1205 const MCOperand &MO2 = MI.getOperand(OpNum+1); in getT2AddrModeSORegOpValue()
1206 const MCOperand &MO3 = MI.getOperand(OpNum+2); in getT2AddrModeSORegOpValue()
1220 getT2AddrModeImm8OpValue(const MCInst &MI, unsigned OpNum, in getT2AddrModeImm8OpValue() argument
1222 const MCOperand &MO1 = MI.getOperand(OpNum); in getT2AddrModeImm8OpValue()
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/external/llvm/lib/CodeGen/
DRegAllocFast.cpp172 LiveRegMap::iterator defineVirtReg(MachineInstr *MI, unsigned OpNum,
174 LiveRegMap::iterator reloadVirtReg(MachineInstr *MI, unsigned OpNum,
177 bool setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg);
576 RAFast::defineVirtReg(MachineInstr *MI, unsigned OpNum, in defineVirtReg() argument
601 LRI->LastOpNum = OpNum; in defineVirtReg()
609 RAFast::reloadVirtReg(MachineInstr *MI, unsigned OpNum, in reloadVirtReg() argument
616 MachineOperand &MO = MI->getOperand(OpNum); in reloadVirtReg()
652 LRI->LastOpNum = OpNum; in reloadVirtReg()
660 bool RAFast::setPhysReg(MachineInstr *MI, unsigned OpNum, unsigned PhysReg) { in setPhysReg() argument
661 MachineOperand &MO = MI->getOperand(OpNum); in setPhysReg()
/external/llvm/lib/Target/X86/
DX86InstrInfo.h348 unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
350 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
355 unsigned OpNum,
DX86InstrInfo.cpp2911 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, in getPartialRegUpdateClearance() argument
2913 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode())) in getPartialRegUpdateClearance()
2934 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, in breakPartialRegDependency() argument
2936 unsigned Reg = MI->getOperand(OpNum).getReg(); in breakPartialRegDependency()
3154 unsigned OpNum = Ops[0]; in canFoldMemoryOperand() local
3164 if (isTwoAddr && NumOps >= 2 && OpNum < 2) { in canFoldMemoryOperand()
3166 } else if (OpNum == 0) { // If operand 0 in canFoldMemoryOperand()
3175 } else if (OpNum == 1) { in canFoldMemoryOperand()
3177 } else if (OpNum == 2) { in canFoldMemoryOperand()
DX86ISelLowering.cpp4539 unsigned NumElems, unsigned &OpNum) { in isShuffleMaskConsecutive() argument
4559 OpNum = SeenV1 ? 0 : 1; in isShuffleMaskConsecutive()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td27 class SDTCisVT<int OpNum, ValueType vt> : SDTypeConstraint<OpNum> {
31 class SDTCisPtrTy<int OpNum> : SDTypeConstraint<OpNum>;
34 class SDTCisInt<int OpNum> : SDTypeConstraint<OpNum>;
37 class SDTCisFP<int OpNum> : SDTypeConstraint<OpNum>;
40 class SDTCisVec<int OpNum> : SDTypeConstraint<OpNum>;
43 class SDTCisSameAs<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
49 class SDTCisVTSmallerThanOp<int OpNum, int OtherOp> : SDTypeConstraint<OpNum> {
DTargetInstrInfo.h59 unsigned OpNum,
788 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum, in getPartialRegUpdateClearance() argument
812 breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum, in breakPartialRegDependency() argument
/external/llvm/lib/Target/Mips/
DMipsAsmPrinter.h65 bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum,
DMipsAsmPrinter.cpp397 unsigned OpNum, unsigned AsmVariant, in PrintAsmMemoryOperand() argument
403 const MachineOperand &MO = MI->getOperand(OpNum); in PrintAsmMemoryOperand()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp68 unsigned OpNum) { in getVEXRegisterEncoding() argument
69 unsigned SrcReg = MI.getOperand(OpNum).getReg(); in getVEXRegisterEncoding()
70 unsigned SrcRegNum = GetX86RegNum(MI.getOperand(OpNum)); in getVEXRegisterEncoding()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp4168 unsigned OpNum = (PFEntry >> 26) & 0x0F; in GeneratePerfectShuffle() local
4185 if (OpNum == OP_COPY) { in GeneratePerfectShuffle()
4196 switch (OpNum) { in GeneratePerfectShuffle()