| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 95 ARMCC::CondCodes Pred, unsigned PredReg, unsigned Scratch,
109 unsigned PredReg,
115 ARMCC::CondCodes Pred, unsigned PredReg,
286 unsigned PredReg, unsigned Scratch, DebugLoc dl, in MergeOps() argument
340 .addImm(Pred).addReg(PredReg).addReg(0); in MergeOps()
351 .addImm(Pred).addReg(PredReg); in MergeOps()
371 ARMCC::CondCodes Pred, unsigned PredReg, in MergeOpsUpdate() argument
416 Pred, PredReg, Scratch, dl, Regs, ImpDefs)) in MergeOpsUpdate()
448 ARMCC::CondCodes Pred, unsigned PredReg, in MergeLDR_STR() argument
501 Base, false, Opcode, Pred, PredReg, Scratch, dl, Merges); in MergeLDR_STR()
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| D | Thumb2InstrInfo.cpp | 60 unsigned PredReg = 0; in ReplaceTailWithBranchTo() local
61 ARMCC::CondCodes CC = getInstrPredicate(Tail, PredReg); in ReplaceTailWithBranchTo()
108 unsigned PredReg = 0; in isLegalToSplitMBBAt() local
109 return getITInstrPredicate(MBBI, PredReg) == ARMCC::AL; in isLegalToSplitMBBAt()
180 ARMCC::CondCodes Pred, unsigned PredReg, in emitT2RegPlusImmediate() argument
195 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
202 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); in emitT2RegPlusImmediate()
211 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
217 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitT2RegPlusImmediate()
403 unsigned PredReg; in rewriteT2FrameIndex() local
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| D | ARMBaseRegisterInfo.cpp | 695 unsigned PredReg, unsigned MIFlags) const { in emitLoadConstPool() argument
705 .addImm(0).addImm(Pred).addReg(PredReg) in emitLoadConstPool()
729 ARMCC::CondCodes Pred = ARMCC::AL, unsigned PredReg = 0) { in emitSPUpdate() argument
732 Pred, PredReg, TII); in emitSPUpdate()
735 Pred, PredReg, TII); in emitSPUpdate()
769 unsigned PredReg = Old->getOperand(2).getReg(); in eliminateCallFramePseudoInstr() local
770 emitSPUpdate(isARM, MBB, I, dl, TII, -Amount, Pred, PredReg); in eliminateCallFramePseudoInstr()
773 unsigned PredReg = Old->getOperand(3).getReg(); in eliminateCallFramePseudoInstr() local
775 emitSPUpdate(isARM, MBB, I, dl, TII, Amount, Pred, PredReg); in eliminateCallFramePseudoInstr()
1108 unsigned PredReg = (PIdx == -1) ? 0 : MI.getOperand(PIdx+1).getReg(); in eliminateFrameIndex() local
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| D | MLxExpansionPass.cpp | 219 unsigned PredReg = MI->getOperand(++NextOp).getReg(); in ExpandFPMLxInstruction() local
230 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
242 MIB.addImm(Pred).addReg(PredReg); in ExpandFPMLxInstruction()
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| D | Thumb2RegisterInfo.h | 37 unsigned PredReg = 0,
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| D | ARMBaseInstrInfo.h | 346 ARMCC::CondCodes getInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
362 ARMCC::CondCodes Pred, unsigned PredReg,
368 ARMCC::CondCodes Pred, unsigned PredReg,
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| D | Thumb2RegisterInfo.cpp | 40 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool() argument
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| D | Thumb1RegisterInfo.h | 42 unsigned PredReg = 0,
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| D | Thumb2InstrInfo.h | 75 ARMCC::CondCodes getITInstrPredicate(const MachineInstr *MI, unsigned &PredReg);
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| D | Thumb2SizeReduction.cpp | 543 unsigned PredReg = 0; in ReduceSpecial() local
544 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { in ReduceSpecial()
642 unsigned PredReg = 0; in ReduceTo2Addr() local
643 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceTo2Addr()
734 unsigned PredReg = 0; in ReduceToNarrow() local
735 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); in ReduceToNarrow()
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| D | Thumb2ITBlockPass.cpp | 173 unsigned PredReg = 0; in InsertITInstructions() local
174 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in InsertITInstructions()
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| D | Thumb1RegisterInfo.cpp | 69 ARMCC::CondCodes Pred, unsigned PredReg, in emitLoadConstPool() argument
79 .addConstantPoolIndex(Idx).addImm(Pred).addReg(PredReg) in emitLoadConstPool()
412 unsigned PredReg; in rewriteFrameIndex() local
413 if (Offset == 0 && getInstrPredicate(&MI, PredReg) == ARMCC::AL) { in rewriteFrameIndex()
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| D | ARMBaseRegisterInfo.h | 168 unsigned PredReg = 0,
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| D | ARMExpandPseudoInsts.cpp | 614 unsigned PredReg = 0; in ExpandMOV32BitImm() local
615 ARMCC::CondCodes Pred = getInstrPredicate(&MI, PredReg); in ExpandMOV32BitImm()
638 LO16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
639 HI16.addImm(Pred).addReg(PredReg).addReg(0); in ExpandMOV32BitImm()
675 LO16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
676 HI16.addImm(Pred).addReg(PredReg); in ExpandMOV32BitImm()
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| D | ARMConstantIslandPass.cpp | 1371 unsigned PredReg = 0; in createNewWater() local
1372 ARMCC::CondCodes CC = getITInstrPredicate(MI, PredReg); in createNewWater()
1818 unsigned PredReg = 0; in optimizeThumb2Branches() local
1819 ARMCC::CondCodes Pred = getInstrPredicate(Br.MI, PredReg); in optimizeThumb2Branches()
1837 Pred = getInstrPredicate(CmpMI, PredReg); in optimizeThumb2Branches()
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| D | ARMBaseInstrInfo.cpp | 1480 llvm::getInstrPredicate(const MachineInstr *MI, unsigned &PredReg) { in getInstrPredicate() argument
1483 PredReg = 0; in getInstrPredicate()
1487 PredReg = MI->getOperand(PIdx+1).getReg(); in getInstrPredicate()
1510 unsigned PredReg = 0; in commuteInstruction() local
1511 ARMCC::CondCodes CC = getInstrPredicate(MI, PredReg); in commuteInstruction()
1513 if (CC == ARMCC::AL || PredReg != ARM::CPSR) in commuteInstruction()
1580 ARMCC::CondCodes Pred, unsigned PredReg, in emitARMRegPlusImmediate() argument
1599 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) in emitARMRegPlusImmediate()
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| D | ARMISelDAGToDAG.cpp | 2599 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2600 SDValue Ops[] = { CPIdx, Pred, PredReg, CurDAG->getEntryNode() }; in Select()
2836 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2837 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
2856 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2857 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
2875 SDValue PredReg = CurDAG->getRegister(0, MVT::i32); in Select() local
2876 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), Pred, PredReg }; in Select()
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