| /external/llvm/include/llvm/MC/ |
| D | MCRegisterInfo.h | 313 int getDwarfRegNum(unsigned RegNum, bool isEH) const { in getDwarfRegNum() argument
317 DwarfLLVMRegPair Key = { RegNum, 0 }; in getDwarfRegNum()
319 if (I == M+Size || I->FromReg != RegNum) in getDwarfRegNum()
326 int getLLVMRegNum(unsigned RegNum, bool isEH) const { in getLLVMRegNum() argument
330 DwarfLLVMRegPair Key = { RegNum, 0 }; in getLLVMRegNum()
332 assert(I != M+Size && I->FromReg == RegNum && "Invalid RegNum"); in getLLVMRegNum()
338 int getSEHRegNum(unsigned RegNum) const { in getSEHRegNum() argument
339 const DenseMap<unsigned, int>::const_iterator I = L2SEHRegs.find(RegNum); in getSEHRegNum()
340 if (I == L2SEHRegs.end()) return (int)RegNum; in getSEHRegNum()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsAsmPrinter.cpp | 213 unsigned RegNum = getMipsRegisterNumbering(Reg); in printSavedRegsBitmask() local
215 FPUBitmask |= (3 << RegNum); in printSavedRegsBitmask()
221 FPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
228 unsigned RegNum = getMipsRegisterNumbering(Reg); in printSavedRegsBitmask() local
229 CPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
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| /external/llvm/lib/Target/MBlaze/AsmParser/ |
| D | MBlazeAsmParser.cpp | 90 unsigned RegNum; member
141 return Reg.RegNum; in getReg()
228 static MBlazeOperand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) { in CreateReg()
230 Op->Reg.RegNum = RegNum; in CreateReg()
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| /external/llvm/lib/CodeGen/ |
| D | RegAllocBase.cpp | 137 unsigned RegNum = I->first; in seedLiveRegs() local
139 if (TargetRegisterInfo::isPhysicalRegister(RegNum)) in seedLiveRegs()
140 PhysReg2LiveUnion[RegNum].unify(VirtReg); in seedLiveRegs()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonHardwareLoops.cpp | 122 unsigned RegNum; member
124 Values(unsigned r) : RegNum(r) {} in Values()
141 return Contents.RegNum; in getReg()
144 Contents.RegNum = Val; in setReg()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeAsmPrinter.cpp | 137 unsigned RegNum = getMBlazeRegisterNumbering(Reg); in printSavedRegsBitmask() local
139 CPUBitmask |= (1 << RegNum); in printSavedRegsBitmask()
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| /external/llvm/lib/Target/X86/ |
| D | X86RegisterInfo.h | 65 int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const;
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| D | X86RegisterInfo.cpp | 80 int X86RegisterInfo::getCompactUnwindRegNum(unsigned RegNum, bool isEH) const { in getCompactUnwindRegNum() argument
81 switch (getLLVMRegNum(RegNum, isEH)) { in getCompactUnwindRegNum()
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| /external/clang/lib/Basic/ |
| D | TargetInfo.cpp | 245 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames) in isValidGCCRegisterName()
298 if (AddlNames[i].Names[j] == Name && AddlNames[i].RegNum < NumNames) in getNormalizedGCCRegisterName()
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| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 342 unsigned RegNum; member
347 unsigned RegNum; member
376 unsigned RegNum; member
506 return Reg.RegNum; in getReg()
1125 .contains(VectorList.RegNum)); in isVecListDPair()
1141 .contains(VectorList.RegNum)); in isVecListDPairSpaced()
1168 .contains(VectorList.RegNum)); in isVecListDPairAllLanes()
1395 unsigned RegNum = getCondCode() == ARMCC::AL ? 0: ARM::CPSR; in addCondCodeOperands() local
1396 Inst.addOperand(MCOperand::CreateReg(RegNum)); in addCondCodeOperands()
1714 Inst.addOperand(MCOperand::CreateReg(PostIdxReg.RegNum)); in addAM3OffsetOperands()
[all …]
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 1161 unsigned RegNum = (IsExtReg ? (1 << 7) : 0); in EncodeInstruction() local
1162 RegNum |= GetX86RegNum(MO) << 4; in EncodeInstruction()
1170 RegNum |= Val; in EncodeInstruction()
1173 EmitImmediate(MCOperand::CreateImm(RegNum), MI.getLoc(), 1, FK_Data_1, in EncodeInstruction()
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| /external/clang/include/clang/Basic/ |
| D | TargetInfo.h | 494 const unsigned RegNum; member
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| /external/llvm/lib/Target/ARM/ |
| D | ARMLoadStoreOptimizer.cpp | 486 unsigned RegNum = MO.isUndef() ? UINT_MAX in MergeLDR_STR() local
493 ((isNotVFP && RegNum > PRegNum) || in MergeLDR_STR()
494 ((Count < Limit) && RegNum == PRegNum+1))) { in MergeLDR_STR()
496 PRegNum = RegNum; in MergeLDR_STR()
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| D | ARMCodeEmitter.cpp | 1393 unsigned RegNum = getARMRegisterNumbering(MO.getReg()); in emitLoadStoreMultipleInstruction() local
1395 RegNum < 16); in emitLoadStoreMultipleInstruction()
1396 Binary |= 0x1 << RegNum; in emitLoadStoreMultipleInstruction()
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| /external/llvm/utils/TableGen/ |
| D | CodeGenRegisters.cpp | 981 unsigned RegNum = Registers[i]->EnumValue; in computeUberSets() local
982 if (AllocatableRegs.count(RegNum)) in computeUberSets()
985 UberSetIDs.join(0, RegNum); in computeUberSets()
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| /external/llvm/lib/Target/ARM/InstPrinter/ |
| D | ARMInstPrinter.cpp | 780 if (unsigned RegNum = MO2.getReg()) in printThumbAddrModeRROperand() local
781 O << ", " << getRegisterName(RegNum); in printThumbAddrModeRROperand()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 1571 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC_SVR4_Custom_AlignArgRegs() local
1577 if (RegNum != NumArgRegs && RegNum % 2 == 1) { in CC_PPC_SVR4_Custom_AlignArgRegs()
1578 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC_SVR4_Custom_AlignArgRegs()
1599 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC_SVR4_Custom_AlignFPArgRegs() local
1603 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC_SVR4_Custom_AlignFPArgRegs()
1604 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC_SVR4_Custom_AlignFPArgRegs()
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