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Searched refs:ShiftAmt (Results 1 – 15 of 15) sorted by relevance

/external/llvm/lib/Transforms/InstCombine/
DInstCombineSimplifyDemanded.cpp583 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in SimplifyDemandedUseBits() local
584 APInt DemandedMaskIn(DemandedMask.lshr(ShiftAmt)); in SimplifyDemandedUseBits()
589 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt+1); in SimplifyDemandedUseBits()
591 DemandedMaskIn |= APInt::getHighBitsSet(BitWidth, ShiftAmt); in SimplifyDemandedUseBits()
597 KnownZero <<= ShiftAmt; in SimplifyDemandedUseBits()
598 KnownOne <<= ShiftAmt; in SimplifyDemandedUseBits()
600 if (ShiftAmt) in SimplifyDemandedUseBits()
601 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt); in SimplifyDemandedUseBits()
607 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in SimplifyDemandedUseBits() local
610 APInt DemandedMaskIn(DemandedMask.shl(ShiftAmt)); in SimplifyDemandedUseBits()
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DInstCombineCasts.cpp560 uint32_t ShiftAmt = KnownZeroMask.logBase2(); in transformZExtICmp() local
562 if (ShiftAmt) { in transformZExtICmp()
565 In = Builder->CreateLShr(In, ConstantInt::get(In->getType(),ShiftAmt), in transformZExtICmp()
929 unsigned ShiftAmt = KnownZeroMask.countTrailingZeros(); in transformSExtICmp() local
931 if (ShiftAmt) in transformSExtICmp()
933 ConstantInt::get(In->getType(), ShiftAmt)); in transformSExtICmp()
943 unsigned ShiftAmt = KnownZeroMask.countLeadingZeros(); in transformSExtICmp() local
945 if (ShiftAmt) in transformSExtICmp()
947 ConstantInt::get(In->getType(), ShiftAmt)); in transformSExtICmp()
/external/llvm/lib/Target/CellSPU/
DSPUISelDAGToDAG.cpp907 SDValue ShiftAmt = N->getOperand(1); in SelectSHLi64() local
908 EVT ShiftAmtVT = ShiftAmt.getValueType(); in SelectSHLi64()
924 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) { in SelectSHLi64()
944 ShiftAmt, in SelectSHLi64()
948 ShiftAmt, in SelectSHLi64()
975 SDValue ShiftAmt = N->getOperand(1); in SelectSRLi64() local
976 EVT ShiftAmtVT = ShiftAmt.getValueType(); in SelectSRLi64()
983 if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(ShiftAmt)) { in SelectSRLi64()
1003 ShiftAmt, in SelectSRLi64()
1007 ShiftAmt, in SelectSRLi64()
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/external/llvm/lib/Analysis/
DValueTracking.cpp475 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); in ComputeMaskedBits() local
478 KnownZero <<= ShiftAmt; in ComputeMaskedBits()
479 KnownOne <<= ShiftAmt; in ComputeMaskedBits()
480 KnownZero |= APInt::getLowBitsSet(BitWidth, ShiftAmt); // low bits known 0 in ComputeMaskedBits()
488 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth); in ComputeMaskedBits() local
493 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt); in ComputeMaskedBits()
494 KnownOne = APIntOps::lshr(KnownOne, ShiftAmt); in ComputeMaskedBits()
496 KnownZero |= APInt::getHighBitsSet(BitWidth, ShiftAmt); in ComputeMaskedBits()
504 uint64_t ShiftAmt = SA->getLimitedValue(BitWidth-1); in ComputeMaskedBits() local
509 KnownZero = APIntOps::lshr(KnownZero, ShiftAmt); in ComputeMaskedBits()
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DConstantFolding.cpp168 unsigned ShiftAmt = isLittleEndian ? 0 : SrcBitSize*(Ratio-1); in FoldBitCast() local
179 ConstantInt::get(Src->getType(), ShiftAmt)); in FoldBitCast()
180 ShiftAmt += isLittleEndian ? SrcBitSize : -SrcBitSize; in FoldBitCast()
200 unsigned ShiftAmt = isLittleEndian ? 0 : DstBitSize*(Ratio-1); in FoldBitCast() local
205 ConstantInt::get(Src->getType(), ShiftAmt)); in FoldBitCast()
206 ShiftAmt += isLittleEndian ? DstBitSize : -DstBitSize; in FoldBitCast()
/external/llvm/lib/Target/ARM/
DARMCodeEmitter.cpp1513 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm(); in emitMiscArithInstruction() local
1515 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!"); in emitMiscArithInstruction()
1516 if (ShiftAmt == 32) in emitMiscArithInstruction()
1517 ShiftAmt = 0; in emitMiscArithInstruction()
1519 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); in emitMiscArithInstruction()
1520 Binary |= ShiftAmt << ARMII::ShiftShift; in emitMiscArithInstruction()
1556 unsigned ShiftAmt = MI.getOperand(3).getImm(); in emitSaturateInstruction() local
1557 if (ShiftAmt == 32 && Opc == ARM_AM::asr) in emitSaturateInstruction()
1558 ShiftAmt = 0; in emitSaturateInstruction()
1559 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!"); in emitSaturateInstruction()
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DARMISelLowering.cpp6910 unsigned ShiftAmt = CountTrailingZeros_64(MulAmt); in PerformMULCombine() local
6912 ShiftAmt = ShiftAmt & (32 - 1); in PerformMULCombine()
6917 MulAmt >>= ShiftAmt; in PerformMULCombine()
6963 if (ShiftAmt != 0) in PerformMULCombine()
6965 Res, DAG.getConstant(ShiftAmt, MVT::i32)); in PerformMULCombine()
/external/llvm/lib/Target/X86/
DX86ISelDAGToDAG.cpp802 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in FoldMaskedShiftToScaledMask() local
803 if (ShiftAmt != 1 && ShiftAmt != 2 && ShiftAmt != 3) in FoldMaskedShiftToScaledMask()
808 SDValue NewMask = DAG.getConstant(Mask >> ShiftAmt, VT); in FoldMaskedShiftToScaledMask()
822 AM.Scale = 1 << ShiftAmt; in FoldMaskedShiftToScaledMask()
862 unsigned ShiftAmt = Shift.getConstantOperandVal(1); in FoldMaskAndShiftToScale() local
879 MaskLZ -= (64 - X.getValueSizeInBits()) + ShiftAmt; in FoldMaskAndShiftToScale()
914 SDValue NewSRLAmt = DAG.getConstant(ShiftAmt + AMShiftAmt, MVT::i8); in FoldMaskAndShiftToScale()
DX86ISelLowering.cpp10257 uint64_t ShiftAmt = C->getZExtValue(); in LowerShift() local
10264 DAG.getConstant(ShiftAmt, MVT::i32)); in LowerShift()
10267 DAG.getConstant(ShiftAmt, MVT::i32)); in LowerShift()
10270 DAG.getConstant(ShiftAmt, MVT::i32)); in LowerShift()
10277 DAG.getConstant(ShiftAmt, MVT::i32)); in LowerShift()
10281 DAG.getConstant(uint8_t(-1U << ShiftAmt), in LowerShift()
10289 DAG.getConstant(ShiftAmt, MVT::i32)); in LowerShift()
10293 DAG.getConstant(uint8_t(-1U) >> ShiftAmt, in LowerShift()
10299 if (ShiftAmt == 7) { in LowerShift()
10307 SmallVector<SDValue, 16> V(16, DAG.getConstant(128 >> ShiftAmt, in LowerShift()
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/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp1079 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); in EmitAtomicBinaryPartword() local
1134 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); in EmitAtomicBinaryPartword()
1138 .addReg(ShiftAmt).addReg(MaskUpper); in EmitAtomicBinaryPartword()
1140 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); in EmitAtomicBinaryPartword()
1201 .addReg(ShiftAmt).addReg(MaskedOldVal1); in EmitAtomicBinaryPartword()
1315 unsigned ShiftAmt = RegInfo.createVirtualRegister(RC); in EmitAtomicCmpSwapPartword() local
1377 BuildMI(BB, dl, TII->get(Mips::SLL), ShiftAmt).addReg(PtrLSB2).addImm(3); in EmitAtomicCmpSwapPartword()
1381 .addReg(ShiftAmt).addReg(MaskUpper); in EmitAtomicCmpSwapPartword()
1386 .addReg(ShiftAmt).addReg(MaskedCmpVal); in EmitAtomicCmpSwapPartword()
1390 .addReg(ShiftAmt).addReg(MaskedNewVal); in EmitAtomicCmpSwapPartword()
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/external/llvm/lib/Transforms/Scalar/
DGVN.cpp1016 unsigned ShiftAmt; in GetStoreValueForLoad() local
1018 ShiftAmt = Offset*8; in GetStoreValueForLoad()
1020 ShiftAmt = (StoreSize-LoadSize-Offset)*8; in GetStoreValueForLoad()
1022 if (ShiftAmt) in GetStoreValueForLoad()
1023 SrcVal = Builder.CreateLShr(SrcVal, ShiftAmt); in GetStoreValueForLoad()
/external/llvm/lib/Support/
DAPInt.cpp2177 unsigned ShiftAmt = (Radix == 16 ? 4 : (Radix == 8 ? 3 : 1)); in toString() local
2183 Tmp = Tmp.lshr(ShiftAmt); in toString()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp629 unsigned ShiftAmt = SVOp->getMaskElt(i); in isVSLDOIShuffleMask() local
630 if (ShiftAmt < i) return -1; in isVSLDOIShuffleMask()
631 ShiftAmt -= i; in isVSLDOIShuffleMask()
636 if (!isConstantOrUndef(SVOp->getMaskElt(i), ShiftAmt+i)) in isVSLDOIShuffleMask()
641 if (!isConstantOrUndef(SVOp->getMaskElt(i), (ShiftAmt+i) & 15)) in isVSLDOIShuffleMask()
644 return ShiftAmt; in isVSLDOIShuffleMask()
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp1607 SDValue ShiftAmt = TLO.DAG.getConstant(BitWidth - ShAmt, ShiftAmtTy); in SimplifyDemandedBits() local
1609 Op.getValueType(), InOp, ShiftAmt)); in SimplifyDemandedBits()
DDAGCombiner.cpp3656 signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue(); in visitSRA() local
3662 if ((ShiftAmt > 0) && in visitSRA()
3667 SDValue Amt = DAG.getConstant(ShiftAmt, in visitSRA()
3814 uint64_t ShiftAmt = N1C->getZExtValue(); in visitSRL() local
3817 DAG.getConstant(ShiftAmt, getShiftAmountTy(SmallVT))); in visitSRL()