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Searched refs:ZERO_EXTEND (Results 1 – 25 of 31) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h361 ZERO_EXTEND, enumerator
/external/llvm/lib/CodeGen/SelectionDAG/
DDAGCombiner.cpp748 Op.getValueType().isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteOperand()
1125 case ISD::ZERO_EXTEND: return visitZERO_EXTEND(N); in visit()
1198 case ISD::ZERO_EXTEND: in combine()
1517 SDValue ZExt = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, N0.getOperand(0)); in visitADD()
2121 N0 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N0); in visitMULHU()
2122 N1 = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N1); in visitMULHU()
2233 SDValue Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(0)); in visitUMUL_LOHI()
2234 SDValue Hi = DAG.getNode(ISD::ZERO_EXTEND, DL, NewVT, N->getOperand(1)); in visitUMUL_LOHI()
2302 if ((N0.getOpcode() == ISD::ZERO_EXTEND || in SimplifyBinOpWithSameOpcodeHands()
2446 SDValue Zext = DAG.getNode(ISD::ZERO_EXTEND, N->getDebugLoc(), in visitAND()
[all …]
DTargetLowering.cpp1018 ExtendKind = ISD::ZERO_EXTEND; in GetReturnInfo()
1195 SDValue Z = DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), X); in ShrinkDemandedOp()
1655 case ISD::ZERO_EXTEND: { in SimplifyDemandedBits()
1704 return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, in SimplifyDemandedBits()
1819 Sign = TLO.DAG.getNode(ISD::ZERO_EXTEND, dl, Op.getValueType(), Sign); in SimplifyDemandedBits()
2003 if (N0->getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC()
2093 if (N0.getOpcode() == ISD::ZERO_EXTEND) { in SimplifySetCC()
2615 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, VT, N0); in SimplifySetCC()
DLegalizeDAG.cpp590 unsigned CastOpc = IdxVT.bitsGT(PtrVT) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; in PerformInsertVectorEltInMemory()
1129 case ISD::ZEXTLOAD: ExtendOp = ISD::ZERO_EXTEND; break; in LegalizeOp()
1351 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); in ExpandExtractFromVectorThroughStack()
1394 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); in ExpandInsertToVectorThroughStack()
2244 DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, in PromoteLegalINT_TO_FP()
3229 { { ISD::MULHU, ISD::UMUL_LOHI, ISD::ZERO_EXTEND }, in ExpandNode()
3304 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0)); in ExpandNode()
3500 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
3522 Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Node->getOperand(0)); in PromoteNode()
3632 ExtOp = isSignedIntSetCC(CCCode) ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteNode()
DLegalizeIntegerTypes.cpp94 case ISD::ZERO_EXTEND: in PromoteIntegerResult()
289 unsigned Opc = VT.isByteSized() ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND; in PromoteIntRes_Constant()
401 if (N->getOpcode() == ISD::ZERO_EXTEND) in PromoteIntRes_INT_EXTEND()
719 SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]); in PromoteIntRes_VAARG()
721 SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]); in PromoteIntRes_VAARG()
788 case ISD::ZERO_EXTEND: Res = PromoteIntOp_ZERO_EXTEND(N); break; in PromoteIntegerOperand()
1123 case ISD::ZERO_EXTEND: ExpandIntRes_ZERO_EXTEND(N, Lo, Hi); break; in ExpandIntegerResult()
2386 Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, N->getOperand(0)); in ExpandIntRes_ZERO_EXTEND()
DSelectionDAG.cpp916 getNode(ISD::ZERO_EXTEND, DL, VT, Op) : in getZExtOrTrunc()
1479 ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND; in getShiftAmountOperand()
1888 case ISD::ZERO_EXTEND: { in ComputeMaskedBits()
2388 case ISD::ZERO_EXTEND: in getNode()
2491 if (OpOpcode == ISD::SIGN_EXTEND || OpOpcode == ISD::ZERO_EXTEND) in getNode()
2497 case ISD::ZERO_EXTEND: in getNode()
2507 if (OpOpcode == ISD::ZERO_EXTEND) // (zext (zext x)) -> (zext x) in getNode()
2508 return getNode(ISD::ZERO_EXTEND, DL, VT, in getNode()
2525 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode()
2551 if (OpOpcode == ISD::ZERO_EXTEND || OpOpcode == ISD::SIGN_EXTEND || in getNode()
[all …]
DLegalizeTypes.cpp989 Index = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Index); in GetVectorElementPointer()
1009 Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo); in JoinIntegers()
DLegalizeVectorTypes.cpp93 case ISD::ZERO_EXTEND: in ScalarizeVectorResult()
507 case ISD::ZERO_EXTEND: in SplitVectorResult()
1002 case ISD::ZERO_EXTEND: in SplitVectorOperand()
1302 case ISD::ZERO_EXTEND: in WidenVectorResult()
2058 case ISD::ZERO_EXTEND: in WidenVectorOperand()
DSelectionDAGDumper.cpp214 case ISD::ZERO_EXTEND: return "zero_extend"; in getOperationName()
DLegalizeVectorOps.cpp197 case ISD::ZERO_EXTEND: in LegalizeOp()
DFastISel.cpp1006 return SelectCast(I, ISD::ZERO_EXTEND); in SelectOperator()
1019 return SelectCast(I, ISD::ZERO_EXTEND); in SelectOperator()
DLegalizeFloatTypes.cpp560 SDValue Op = DAG.getNode(Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in SoftenFloatRes_XINT_TO_FP()
1180 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in ExpandFloatRes_XINT_TO_FP()
1187 Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl, in ExpandFloatRes_XINT_TO_FP()
DLegalizeTypesGeneric.cpp188 Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx); in ExpandRes_EXTRACT_VECTOR_ELT()
DSelectionDAGBuilder.cpp155 Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, TotalVT, Lo); in getCopyFromParts()
1208 ExtendKind = ISD::ZERO_EXTEND; in visitRet()
1228 else if (ExtendKind == ISD::ZERO_EXTEND) in visitRet()
2600 Op2 = DAG.getNode(ISD::ZERO_EXTEND, DL, ShiftTy, Op2); in visitShift()
2702 setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); in visitZExt()
2789 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), in visitInsertElement()
2799 SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), in visitExtractElement()
6430 ExtendKind = ISD::ZERO_EXTEND; in LowerCallTo()
/external/llvm/lib/Target/ARM/
DARMSelectionDAGInfo.cpp173 Src = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src); in EmitTargetCodeForMemset()
DARMISelLowering.cpp551 setTargetDAGCombine(ISD::ZERO_EXTEND); in ARMTargetLowering()
1359 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
3178 CastOpc = ISD::ZERO_EXTEND; in LowerVectorINT_TO_FP()
4757 if (N->getOpcode() == ISD::ZERO_EXTEND || ISD::isZEXTLoad(N)) in isZeroExtended()
4767 if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) in SkipExtension()
5008 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N0); in LowerUDIV()
5009 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v8i16, N1); in LowerUDIV()
5035 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N0); in LowerUDIV()
5036 N1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::v4i32, N1); in LowerUDIV()
8244 case ISD::ZERO_EXTEND: in PerformExtendCombine()
[all …]
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp466 setTargetDAGCombine(ISD::ZERO_EXTEND); in SPUTargetLowering()
739 result = DAG.getNode(ISD::ZERO_EXTEND, dl, OutVT, result); in LowerLOAD()
2097 Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Elt); in LowerEXTRACT_VECTOR_ELT()
2230 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0); in LowerI8Math()
2233 ? ISD::ZERO_EXTEND in LowerI8Math()
2253 N0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, N0); in LowerI8Math()
2255 unsigned N1Opc = ISD::ZERO_EXTEND; in LowerI8Math()
2964 case ISD::ZERO_EXTEND: in PerformDAGCombine()
3039 case ISD::ZERO_EXTEND: in PerformDAGCombine()
DSPUISelDAGToDAG.cpp640 } else if ((Opc == ISD::ZERO_EXTEND || Opc == ISD::ANY_EXTEND) in Select()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp791 unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : in X86SelectRet()
1005 ResultReg = FastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, in X86SelectZExt()
1710 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in DoSelectCall()
1722 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), in DoSelectCall()
DX86ISelLowering.cpp765 setOperationAction(ISD::ZERO_EXTEND, (MVT::SimpleValueType)VT, Expand); in X86TargetLowering()
1225 setTargetDAGCombine(ISD::ZERO_EXTEND); in X86TargetLowering()
1619 if (Subtarget->is64Bit() && VT == MVT::i1 && ExtendKind == ISD::ZERO_EXTEND) in getTypeForExtArgOrReturn()
2232 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); in LowerCall()
4672 LastElt = DAG.getNode(ISD::ZERO_EXTEND, dl, in LowerBuildVectorv16i8()
4676 ThisElt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Op.getOperand(i)); in LowerBuildVectorv16i8()
5136 Item = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Item); in LowerBUILD_VECTOR()
9338 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
9666 return DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, SetCC); in LowerINTRINSIC_WO_CHAIN()
10065 ISD::TRUNCATE : ISD::ZERO_EXTEND), DL, VT, RetVal); in LowerFLT_ROUNDS_()
[all …]
DX86ISelDAGToDAG.cpp909 SDValue NewX = DAG.getNode(ISD::ZERO_EXTEND, X.getDebugLoc(), VT, X); in FoldMaskAndShiftToScale()
1125 (RHS.getNode()->getOpcode() == ISD::ZERO_EXTEND && in MatchAddressRecursively()
/external/llvm/include/llvm/Target/
DTargetLowering.h115 return ISD::ZERO_EXTEND; in getExtendForContent()
/external/llvm/lib/Target/MBlaze/
DMBlazeISelLowering.cpp733 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, RegVT, Arg); in LowerCall()
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp1833 E = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, E); in LowerFCOPYSIGN64()
1853 SrlY = DAG.getNode(ISD::ZERO_EXTEND, DL, TyX, SrlY); in LowerFCOPYSIGN64()
2463 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, LocVT, Arg); in LowerCall()
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp476 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()

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