| /external/tremolo/Tremolo/ |
| D | bitwiseARM.s | 75 BEQ look_next_segment @ r10= r12 = 0, if we branch
96 BEQ look_out_of_data
102 BEQ look_next_segment_2
142 BEQ look_out_of_data
185 BEQ adv_end
267 BEQ read_next_segment @ r10= r12 = 0, if we branch
290 BEQ read_out_of_data
298 BEQ read_next_segment_2
382 BEQ read_out_of_data
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| D | dpen.s | 59 BEQ dpen_nobits
90 BEQ meth3
93 BEQ meth1
278 BEQ dm2
462 BEQ _cs_end
472 BEQ _cs_no_bytes
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| D | mdctLARM.s | 283 BEQ sr_end
303 BEQ find_shift_loop
1107 BEQ mdct_end
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| D | mdctARM.s | 280 BEQ sr_end
300 BEQ find_shift_loop
1121 BEQ mdct_end
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| /external/v8/src/mips/ |
| D | constants-mips.cc | 155 case BEQ: in IsForbiddenInBranchDelay()
307 case BEQ: in InstructionType()
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| D | constants-mips.h | 258 BEQ = ((0 << 3) + 4) << kOpcodeShift, enumerator
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| D | disasm-mips.cc | 833 case BEQ: in DecodeTypeImmediate()
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| D | assembler-mips.cc | 507 return opcode == BEQ || in IsBranch()
523 return GetOpcodeField(instr) == BEQ; in IsBeq()
1072 GenInstrImmediate(BEQ, rs, rt, offset); in beq()
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| D | code-stubs-mips.h | 507 masm->instr_at_put(pos, BEQ | (zero_reg.code() << kRsShift) | in PatchNopIntoBranch()
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| D | simulator-mips.cc | 2394 case BEQ: in DecodeTypeImmediate()
2530 case BEQ: in DecodeTypeImmediate()
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| D | macro-assembler-mips.cc | 5417 ASSERT(opcode == BEQ || in ChangeBranchCondition()
5425 opcode = (cond == eq) ? BEQ : BNE; in ChangeBranchCondition()
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| /external/aac/libSBRdec/src/arm/ |
| D | env_calc_arm.cpp | 121 BEQ FDK_get_maxval_loop_end in FDK_get_maxval()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEInstrInfo.cpp | 234 case Mips::BEQ: return Mips::BNE; in GetOppositeBranchOpc()
235 case Mips::BNE: return Mips::BEQ; in GetOppositeBranchOpc()
311 return (Opc == Mips::BEQ || Opc == Mips::BNE || Opc == Mips::BGTZ || in GetAnalyzableBrOpc()
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| D | MipsInstrInfo.td | 1010 def BEQ : CBranch<0x04, "beq", seteq, CPURegs>;
1214 (BEQ (SLTOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1216 (BEQ (SLTuOp RC:$lhs, RC:$rhs), ZERO, bb:$dst)>;
1218 (BEQ (SLTiOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1220 (BEQ (SLTiuOp RC:$lhs, immSExt16:$rhs), ZERO, bb:$dst)>;
1223 (BEQ (SLTOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1225 (BEQ (SLTuOp RC:$rhs, RC:$lhs), ZERO, bb:$dst)>;
1231 defm : BrcondPats<CPURegs, BEQ, BNE, SLT, SLTu, SLTi, SLTiu, ZERO>;
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| D | MipsISelLowering.cpp | 1046 unsigned LL, SC, AND, NOR, ZERO, BEQ; in EmitAtomicBinary() local
1054 BEQ = Mips::BEQ; in EmitAtomicBinary()
1062 BEQ = Mips::BEQ64; in EmitAtomicBinary()
1114 BuildMI(BB, dl, TII->get(BEQ)).addReg(Success).addReg(ZERO).addMBB(loopMBB); in EmitAtomicBinary()
1250 BuildMI(BB, dl, TII->get(Mips::BEQ)) in EmitAtomicBinaryPartword()
1286 unsigned LL, SC, ZERO, BNE, BEQ; in EmitAtomicCmpSwap() local
1293 BEQ = Mips::BEQ; in EmitAtomicCmpSwap()
1300 BEQ = Mips::BEQ64; in EmitAtomicCmpSwap()
1349 BuildMI(BB, dl, TII->get(BEQ)) in EmitAtomicCmpSwap()
1478 BuildMI(BB, dl, TII->get(Mips::BEQ)) in EmitAtomicCmpSwapPartword()
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| /external/llvm/test/CodeGen/Mips/ |
| D | 2011-05-26-BranchKillsVreg.ll | 5 ; This requires updating the BNE-J terminators to a BEQ. The BNE instruction
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.cpp | 247 case MBlaze::BEQ: Cond[0].setImm(MBlaze::BNE); return false; in ReverseBranchCondition()
248 case MBlaze::BNE: Cond[0].setImm(MBlaze::BEQ); return false; in ReverseBranchCondition()
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| D | MBlazeInstrFormats.td | 20 def FCRR : Format<3>; // PUTD, WDC, WIC, BEQ, BNE, BGE, etc.
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| D | MBlazeInstrInfo.td | 507 def BEQ : BranchC<0x27, 0x00, 0x000, "beq ">;
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| /external/llvm/lib/Target/MBlaze/Disassembler/ |
| D | MBlazeDisassembler.cpp | 51 MBlaze::SEXT8, MBlaze::MFS, MBlaze::BR, MBlaze::BEQ, //24,25,26,27
133 case 0x00: return MBlaze::BEQ; in decodeBEQ()
469 case MBlaze::BEQ: return decodeBEQ(insn); in getOPCODE()
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