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Searched refs:BaseOffs (Results 1 – 15 of 15) sorted by relevance

/external/llvm/lib/Transforms/Utils/
DAddrModeMatcher.cpp39 if (BaseOffs) in print()
40 OS << (NeedPlus ? " + " : "") << BaseOffs, NeedPlus = true; in print()
106 TestAddrMode.BaseOffs += CI->getSExtValue()*TestAddrMode.Scale; in MatchScaledValue()
251 AddrMode.BaseOffs += ConstantOffset; in MatchOperationAddr()
257 AddrMode.BaseOffs -= ConstantOffset; in MatchOperationAddr()
266 AddrMode.BaseOffs += ConstantOffset; in MatchOperationAddr()
291 AddrMode.BaseOffs += ConstantOffset; in MatchOperationAddr()
315 AddrMode.BaseOffs += CI->getSExtValue(); in MatchAddr()
318 AddrMode.BaseOffs -= CI->getSExtValue(); in MatchAddr()
/external/llvm/lib/Transforms/Scalar/
DLoopStrengthReduce.cpp388 if (AM.BaseOffs != 0) { in print()
390 OS << AM.BaseOffs; in print()
929 int64_t Offset = (uint64_t)*I + F.AM.BaseOffs; in RateFormula()
1282 return !AM.BaseGV && AM.BaseOffs == 0 && AM.Scale <= 1; in isLegalUse()
1291 if (AM.Scale != 0 && AM.HasBaseReg && AM.BaseOffs != 0) in isLegalUse()
1301 if (AM.BaseOffs != 0) { in isLegalUse()
1308 int64_t Offs = AM.BaseOffs; in isLegalUse()
1319 return !AM.BaseGV && AM.Scale == 0 && AM.BaseOffs == 0; in isLegalUse()
1323 return !AM.BaseGV && (AM.Scale == 0 || AM.Scale == -1) && AM.BaseOffs == 0; in isLegalUse()
1334 if (((int64_t)((uint64_t)AM.BaseOffs + MinOffset) > AM.BaseOffs) != in isLegalUse()
[all …]
DCodeGenPrepare.cpp980 if (AddrMode.BaseOffs) { in OptimizeMemoryInst()
981 Value *V = ConstantInt::get(IntPtrTy, AddrMode.BaseOffs); in OptimizeMemoryInst()
/external/llvm/include/llvm/Transforms/Utils/
DAddrModeMatcher.h45 (BaseGV == O.BaseGV) && (BaseOffs == O.BaseOffs) &&
/external/llvm/lib/Analysis/
DBasicAliasAnalysis.cpp234 DecomposeGEPExpression(const Value *V, int64_t &BaseOffs, in DecomposeGEPExpression() argument
240 BaseOffs = 0; in DecomposeGEPExpression()
301 BaseOffs += TD->getStructLayout(STy)->getElementOffset(FieldNo); in DecomposeGEPExpression()
308 BaseOffs += TD->getTypeAllocSize(*GTI)*CIdx->getSExtValue(); in DecomposeGEPExpression()
328 BaseOffs += IndexOffset.getSExtValue()*Scale; in DecomposeGEPExpression()
/external/llvm/lib/Target/XCore/
DXCoreISelLowering.cpp1571 return AM.Scale == 0 && isImmUs(AM.BaseOffs) && isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1577 AM.BaseOffs%4 == 0; in isLegalAddressingMode()
1584 return isImmUs(AM.BaseOffs); in isLegalAddressingMode()
1587 return AM.Scale == 1 && AM.BaseOffs == 0; in isLegalAddressingMode()
1592 return isImmUs2(AM.BaseOffs); in isLegalAddressingMode()
1595 return AM.Scale == 2 && AM.BaseOffs == 0; in isLegalAddressingMode()
1599 return isImmUs4(AM.BaseOffs); in isLegalAddressingMode()
1602 return AM.Scale == 4 && AM.BaseOffs == 0; in isLegalAddressingMode()
/external/llvm/include/llvm/Target/
DTargetLowering.h1623 int64_t BaseOffs; member
1626 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} in AddrMode()
/external/llvm/lib/CodeGen/SelectionDAG/
DTargetLowering.cpp3264 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
3276 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
3281 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
DDAGCombiner.cpp6738 AM.BaseOffs = Offset->getSExtValue(); in canFoldInAddressingMode()
6746 AM.BaseOffs = -Offset->getSExtValue(); in canFoldInAddressingMode()
/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp1556 if (AM.BaseOffs <= -(1LL << 13) || AM.BaseOffs >= (1LL << 13)-1) { in isLegalAddressingMode()
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp3254 if (AM.BaseGV && !AM.HasBaseReg && AM.Scale == 0 && AM.BaseOffs == 0) in isLegalAddressingMode()
3258 if (AM.BaseGV ==0 && AM.HasBaseReg && AM.Scale == 0 && isInt<14>(AM.BaseOffs)) in isLegalAddressingMode()
3262 if (AM.BaseGV == 0 && AM.HasBaseReg && AM.Scale == 1 && AM.BaseOffs ==0) in isLegalAddressingMode()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp1216 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale) in isLegalAddressingMode()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp5824 if (AM.BaseOffs <= -(1LL << 16) || AM.BaseOffs >= (1LL << 16)-1) in isLegalAddressingMode()
5836 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
5841 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp9214 if (!isLegalAddressImmediate(AM.BaseOffs, VT, Subtarget)) in isLegalAddressingMode()
9230 if (AM.BaseOffs) in isLegalAddressingMode()
/external/llvm/lib/Target/X86/
DX86ISelLowering.cpp11677 if (!X86::isOffsetSuitableForCodeModel(AM.BaseOffs, M, AM.BaseGV != NULL)) in isLegalAddressingMode()
11695 Subtarget->is64Bit() && (AM.BaseOffs || AM.Scale > 1)) in isLegalAddressingMode()