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Searched refs:CondCode (Results 1 – 25 of 39) sorted by relevance

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/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h724 enum CondCode { enum
757 inline bool isSignedIntSetCC(CondCode Code) { in isSignedIntSetCC()
763 inline bool isUnsignedIntSetCC(CondCode Code) { in isUnsignedIntSetCC()
770 inline bool isTrueWhenEqual(CondCode Cond) { in isTrueWhenEqual()
778 inline unsigned getUnorderedFlavor(CondCode Cond) { in getUnorderedFlavor()
784 CondCode getSetCCInverse(CondCode Operation, bool isInteger);
788 CondCode getSetCCSwappedOperands(CondCode Operation);
794 CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, bool isInteger);
800 CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, bool isInteger);
DAnalysis.h72 ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred);
76 ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC);
81 ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred);
DSelectionDAG.h481 SDValue getCondCode(ISD::CondCode Cond);
609 ISD::CondCode Cond) {
621 SDValue True, SDValue False, ISD::CondCode Cond) {
985 SDValue N2, ISD::CondCode Cond, DebugLoc dl);
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp32 enum CondCode { enum
130 static XCore::CondCode GetCondFromBranchOpc(unsigned BrOpc) in GetCondFromBranchOpc()
143 static inline unsigned GetCondBranchFromCond(XCore::CondCode CC) in GetCondBranchFromCond()
154 static inline XCore::CondCode GetOppositeBranchCondition(XCore::CondCode CC) in GetOppositeBranchCondition()
214 XCore::CondCode BranchCode = GetCondFromBranchOpc(LastInst->getOpcode()); in AnalyzeBranch()
236 XCore::CondCode BranchCode = GetCondFromBranchOpc(SecondLastOpc); in AnalyzeBranch()
290 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
299 unsigned Opc = GetCondBranchFromCond((XCore::CondCode)Cond[0].getImm()); in InsertBranch()
404 Cond[0].setImm(GetOppositeBranchCondition((XCore::CondCode)Cond[0].getImm())); in ReverseBranchCondition()
/external/llvm/lib/Target/MBlaze/
DMBlazeInstrInfo.h39 enum CondCode { enum
89 inline static unsigned GetCondBranchFromCond(CondCode CC) { in GetCondBranchFromCond()
106 inline static const char *MBlazeFCCToString(MBlaze::CondCode CC) { in MBlazeFCCToString()
/external/llvm/lib/Target/Mips/InstPrinter/
DMipsInstPrinter.h33 enum CondCode { enum
73 const char *MipsFCCToString(Mips::CondCode CC);
DMipsInstPrinter.cpp28 const char* Mips::MipsFCCToString(Mips::CondCode CC) { in MipsFCCToString()
198 O << MipsFCCToString((Mips::CondCode)MO.getImm()); in printFCCOperand()
/external/llvm/lib/Target/X86/
DX86InstrInfo.h32 enum CondCode { enum
62 unsigned GetCondBranchFromCond(CondCode CC);
66 CondCode GetOppositeBranchCondition(X86::CondCode CC);
DX86InstrInfo.cpp2223 static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) { in getCondFromBranchOpc()
2246 static X86::CondCode getCondFromSETOpc(unsigned Opc) { in getCondFromSETOpc()
2269 static X86::CondCode getCondFromCMovOpc(unsigned Opc) { in getCondFromCMovOpc()
2323 unsigned X86::GetCondBranchFromCond(X86::CondCode CC) { in GetCondBranchFromCond()
2347 X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) { in GetOppositeBranchCondition()
2372 static X86::CondCode getSwappedCondition(X86::CondCode CC) { in getSwappedCondition()
2390 static unsigned getSETFromCond(X86::CondCode CC, in getSETFromCond()
2417 static unsigned getCMovFromCond(X86::CondCode CC, unsigned RegBytes, in getCMovFromCond()
2530 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode()); in AnalyzeBranch()
2592 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm(); in AnalyzeBranch()
[all …]
DX86ISelLowering.cpp3070 static unsigned TranslateX86CC(ISD::CondCode SetCCOpcode, bool isFP, in TranslateX86CC()
8600 SDValue X86TargetLowering::LowerToBT(SDValue And, ISD::CondCode CC, in LowerToBT()
8677 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in LowerSETCC()
8702 X86::CondCode CCode = (X86::CondCode)Op0.getConstantOperandVal(0); in LowerSETCC()
8761 ISD::CondCode SetCCOpcode = cast<CondCodeSDNode>(CC)->get(); in LowerVSETCC()
8957 unsigned CondCode =cast<ConstantSDNode>(Cond.getOperand(0))->getZExtValue(); in LowerSELECT() local
8960 (CondCode == X86::COND_E || CondCode == X86::COND_NE)) { in LowerSELECT()
8969 (isAllOnes(Op1) == (CondCode == X86::COND_NE))) { in LowerSELECT()
8988 if (isAllOnes(Op1) != (CondCode == X86::COND_E)) in LowerSELECT()
9090 unsigned CondCode = cast<ConstantSDNode>(CC)->getZExtValue(); in LowerSELECT() local
[all …]
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td497 class CondCode; // ISD::CondCode enums
498 def SETOEQ : CondCode; def SETOGT : CondCode;
499 def SETOGE : CondCode; def SETOLT : CondCode; def SETOLE : CondCode;
500 def SETONE : CondCode; def SETO : CondCode; def SETUO : CondCode;
501 def SETUEQ : CondCode; def SETUGT : CondCode; def SETUGE : CondCode;
502 def SETULT : CondCode; def SETULE : CondCode; def SETUNE : CondCode;
504 def SETEQ : CondCode; def SETGT : CondCode; def SETGE : CondCode;
505 def SETLT : CondCode; def SETLE : CondCode; def SETNE : CondCode;
DTargetLowering.h495 getCondCodeAction(ISD::CondCode CC, EVT VT) const { in getCondCodeAction()
507 bool isCondCodeLegal(ISD::CondCode CC, EVT VT) const { in isCondCodeLegal()
942 ISD::CondCode Cond, bool foldBooleans,
1151 void setCondCodeAction(ISD::CondCode CC, MVT VT, in setCondCodeAction()
1746 void setCmpLibcallCC(RTLIB::Libcall Call, ISD::CondCode CC) { in setCmpLibcallCC()
1752 ISD::CondCode getCmpLibcallCC(RTLIB::Libcall Call) const { in getCmpLibcallCC()
2081 ISD::CondCode CmpLibcallCCs[RTLIB::UNKNOWN_LIBCALL];
/external/llvm/lib/CodeGen/
DAnalysis.cpp152 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { in getFCmpCondCode()
174 ISD::CondCode llvm::getFCmpCodeWithoutNaN(ISD::CondCode CC) { in getFCmpCodeWithoutNaN()
189 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) { in getICmpCondCode()
/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp101 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
463 ISD::CondCode CC, DebugLoc dl) { in SelectCC()
560 static PPC::Predicate getPredicateForSetCC(ISD::CondCode CC) { in getPredicateForSetCC()
594 static unsigned getCRIdxForSetCC(ISD::CondCode CC, bool &Invert, int &Other) { in getCRIdxForSetCC()
627 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get(); in SelectSETCC()
1060 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(4))->get(); in Select()
1114 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(1))->get(); in Select()
1115 SDValue CondCode = SelectCC(N->getOperand(2), N->getOperand(3), CC, dl); in Select() local
1116 SDValue Ops[] = { getI32Imm(getPredicateForSetCC(CC)), CondCode, in Select()
/external/llvm/lib/Target/Mips/Disassembler/
DMipsDisassembler.cpp437 int CondCode = Insn & 0xf; in DecodeCondCode() local
438 Inst.addOperand(MCOperand::CreateImm(CondCode)); in DecodeCondCode()
/external/llvm/lib/CodeGen/SelectionDAG/
DLegalizeFloatTypes.cpp613 ISD::CondCode &CCCode, DebugLoc dl) { in SoftenSetCCOperands()
714 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); in SoftenFloatOp_BR_CC()
756 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); in SoftenFloatOp_SELECT_CC()
775 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); in SoftenFloatOp_SETCC()
1295 ISD::CondCode &CCCode, in FloatExpandSetCCOperands()
1325 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(1))->get(); in ExpandFloatOp_BR_CC()
1406 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(4))->get(); in ExpandFloatOp_SELECT_CC()
1424 ISD::CondCode CCCode = cast<CondCodeSDNode>(N->getOperand(2))->get(); in ExpandFloatOp_SETCC()
DLegalizeTypes.h290 void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
364 ISD::CondCode &CCCode, DebugLoc dl);
437 ISD::CondCode &CCCode, DebugLoc dl);
493 ISD::CondCode &CCCode, DebugLoc dl);
DSelectionDAGBuilder.h197 CaseBlock(ISD::CondCode cc, const Value *cmplhs, const Value *cmprhs,
207 ISD::CondCode CC;
DSelectionDAG.cpp240 ISD::CondCode ISD::getSetCCSwappedOperands(ISD::CondCode Operation) { in getSetCCSwappedOperands()
245 return ISD::CondCode((Operation & ~6) | // Keep the N, U, E bits in getSetCCSwappedOperands()
252 ISD::CondCode ISD::getSetCCInverse(ISD::CondCode Op, bool isInteger) { in getSetCCInverse()
262 return ISD::CondCode(Operation); in getSetCCInverse()
269 static int isSignedOp(ISD::CondCode Opcode) { in isSignedOp()
289 ISD::CondCode ISD::getSetCCOrOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCOrOperation()
306 return ISD::CondCode(Op); in getSetCCOrOperation()
313 ISD::CondCode ISD::getSetCCAndOperation(ISD::CondCode Op1, ISD::CondCode Op2, in getSetCCAndOperation()
320 ISD::CondCode Result = ISD::CondCode(Op1 & Op2); in getSetCCAndOperation()
1287 SDValue SelectionDAG::getCondCode(ISD::CondCode Cond) { in getCondCode()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp664 ISD::CondCode CC, in EmitCMP()
748 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
780 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in LowerSETCC()
847 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp649 static SPCC::CondCodes IntCondCCodeToICC(ISD::CondCode CC) { in IntCondCCodeToICC()
667 static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) { in FPCondCCodeToFCC()
866 ISD::CondCode CC, unsigned &SPCC) { in LookThroughSetCC()
945 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get(); in LowerBR_CC()
978 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get(); in LowerSELECT_CC()
/external/llvm/lib/Target/ARM/
DARMISelLowering.cpp1087 static ARMCC::CondCodes IntCCToARMCC(ISD::CondCode CC) { in IntCCToARMCC()
1104 static void FPCCToARMCC(ISD::CondCode CC, ARMCC::CondCodes &CondCode, in FPCCToARMCC() argument
1110 case ISD::SETOEQ: CondCode = ARMCC::EQ; break; in FPCCToARMCC()
1112 case ISD::SETOGT: CondCode = ARMCC::GT; break; in FPCCToARMCC()
1114 case ISD::SETOGE: CondCode = ARMCC::GE; break; in FPCCToARMCC()
1115 case ISD::SETOLT: CondCode = ARMCC::MI; break; in FPCCToARMCC()
1116 case ISD::SETOLE: CondCode = ARMCC::LS; break; in FPCCToARMCC()
1117 case ISD::SETONE: CondCode = ARMCC::MI; CondCode2 = ARMCC::GT; break; in FPCCToARMCC()
1118 case ISD::SETO: CondCode = ARMCC::VC; break; in FPCCToARMCC()
1119 case ISD::SETUO: CondCode = ARMCC::VS; break; in FPCCToARMCC()
[all …]
DARMISelLowering.h505 SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
/external/llvm/lib/Target/Mips/
DMipsISelLowering.cpp535 static Mips::CondCode FPCondCCodeToFCC(ISD::CondCode CC) { in FPCondCCodeToFCC()
563 static bool InvertFPCondCode(Mips::CondCode CC) { in InvertFPCondCode()
590 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); in CreateFPCmp()
599 bool invert = InvertFPCondCode((Mips::CondCode) in CreateCMovFP()
631 ISD::CondCode CC = cast<CondCodeSDNode>(SetCC.getOperand(2))->get(); in PerformSELECTCombine()
835 static Mips::FPBranchCode GetFPBranchCodeFromCond(Mips::CondCode CC) { in GetFPBranchCodeFromCond()
1519 Mips::CondCode CC = in LowerBRCOND()
1520 (Mips::CondCode)cast<ConstantSDNode>(CCNode)->getZExtValue(); in LowerBRCOND()
DMipsAsmPrinter.cpp528 O << Mips::MipsFCCToString((Mips::CondCode)MO.getImm()); in printFCCOperand()

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