Searched refs:ImplicitDefine (Results 1 – 8 of 8) sorted by relevance
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 39 ImplicitDefine = Implicit | Define, enumerator
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| /external/llvm/lib/Target/ARM/ |
| D | ARMExpandPseudoInsts.cpp | 428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
570 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
967 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandMI()
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| D | ARMFrameLowering.cpp | 925 .addReg(SupReg, RegState::ImplicitDefine)); in emitAlignedDPRCS2Restores()
940 .addReg(SupReg, RegState::ImplicitDefine)); in emitAlignedDPRCS2Restores()
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| D | ARMBaseInstrInfo.cpp | 993 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1014 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
1034 MIB.addReg(DestReg, RegState::ImplicitDefine); in loadRegFromStackSlot()
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| D | ARMLoadStoreOptimizer.cpp | 358 MIB.addReg(ImpDefs[i], RegState::ImplicitDefine); in MergeOps()
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| D | ARMISelLowering.cpp | 6265 MIB.addReg(Reg, RegState::ImplicitDefine | RegState::Dead); in EmitSjLjDispatchBlock()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 12774 .addReg(X86::RAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
12782 .addReg(X86::EAX, RegState::ImplicitDefine); in EmitLoweredSegAlloca()
12895 MIB.addReg(X86::RAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
12906 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
12917 MIB.addReg(X86::EAX, RegState::ImplicitDefine).addRegMask(RegMask); in EmitLoweredTLSCall()
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| D | X86InstrInfo.cpp | 3784 .addReg(Reg, RegState::ImplicitDefine); in breakPartialRegDependency()
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