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Searched refs:MCID (Results 1 – 25 of 42) sorted by relevance

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/external/llvm/include/llvm/MC/
DMCInstrDesc.h96 namespace MCID {
190 return Flags & (1 << MCID::Variadic); in isVariadic()
196 return Flags & (1 << MCID::HasOptionalDef); in hasOptionalDef()
203 return Flags & (1 << MCID::Pseudo); in isPseudo()
207 return Flags & (1 << MCID::Return); in isReturn()
211 return Flags & (1 << MCID::Call); in isCall()
218 return Flags & (1 << MCID::Barrier); in isBarrier()
228 return Flags & (1 << MCID::Terminator); in isTerminator()
236 return Flags & (1 << MCID::Branch); in isBranch()
242 return Flags & (1 << MCID::IndirectBranch); in isIndirectBranch()
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/external/llvm/include/llvm/CodeGen/
DMachineInstr.h65 const MCInstrDesc *MCID; // Instruction descriptor.
108 explicit MachineInstr(const MCInstrDesc &MCID, bool NoImp = false);
113 MachineInstr(MachineBasicBlock *MBB, const MCInstrDesc &MCID);
118 explicit MachineInstr(const MCInstrDesc &MCID, const DebugLoc dl,
125 const MCInstrDesc &MCID);
254 const MCInstrDesc &getDesc() const { return *MCID; }
258 int getOpcode() const { return MCID->Opcode; }
326 return hasProperty(MCID::Variadic, Type);
332 return hasProperty(MCID::HasOptionalDef, Type);
339 return hasProperty(MCID::Pseudo, Type);
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DMachineInstrBuilder.h197 const MCInstrDesc &MCID) { in BuildMI() argument
198 return MachineInstrBuilder(MF.CreateMachineInstr(MCID, DL)); in BuildMI()
206 const MCInstrDesc &MCID, in BuildMI() argument
208 return MachineInstrBuilder(MF.CreateMachineInstr(MCID, DL)) in BuildMI()
219 const MCInstrDesc &MCID, in BuildMI() argument
221 MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL); in BuildMI()
229 const MCInstrDesc &MCID, in BuildMI() argument
231 MachineInstr *MI = BB.getParent()->CreateMachineInstr(MCID, DL); in BuildMI()
239 const MCInstrDesc &MCID, in BuildMI() argument
243 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
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/external/llvm/lib/Target/ARM/
DARMCodeEmitter.cpp101 const MCInstrDesc &MCID,
107 const MCInstrDesc &MCID) const;
279 const MCInstrDesc &MCID = MI.getDesc(); in getHiLo16ImmOpValue() local
282 unsigned Reloc = (MCID.Opcode == ARM::MOVi16 ? in getHiLo16ImmOpValue()
481 const MCInstrDesc &MCID = MI.getDesc(); in getMachineOpValue() local
483 unsigned Reloc = ((MCID.TSFlags & ARMII::FormMask) == ARMII::VFPLdStFrm) in getMachineOpValue()
817 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelInstruction() local
825 Binary |= getAddrModeSBit(MI, MCID); in emitLEApcrelInstruction()
844 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelJTInstruction() local
853 Binary |= getAddrModeSBit(MI, MCID); in emitLEApcrelJTInstruction()
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DThumb2SizeReduction.cpp192 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { in HasImplicitCPSRDef() argument
193 for (const uint16_t *Regs = MCID.getImplicitDefs(); *Regs; ++Regs) in HasImplicitCPSRDef()
512 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial() local
513 if (MCID.hasOptionalDef() && in ReduceSpecial()
514 MI->getOperand(MCID.getNumOperands()-1).getReg() == ARM::CPSR) in ReduceSpecial()
656 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr() local
657 if (MCID.hasOptionalDef()) { in ReduceTo2Addr()
658 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr()
684 unsigned NumOps = MCID.getNumOperands(); in ReduceTo2Addr()
686 if (i < NumOps && MCID.OpInfo[i].isOptionalDef()) in ReduceTo2Addr()
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DARMHazardRecognizer.cpp22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
23 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
26 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType() local
44 if (LastMI && (MCID.TSFlags & ARMII::DomainMask) != ARMII::DomainGeneral) { in getHazardType()
DMLxExpansionPass.cpp140 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard() local
141 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in hasRAWHazard()
144 unsigned Opcode = MCID.getOpcode(); in hasRAWHazard()
278 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions() local
286 unsigned Domain = MCID.TSFlags & ARMII::DomainMask; in ExpandFPMLxInstructions()
296 if (!TII->isFpMLxInstruction(MCID.getOpcode(), in ExpandFPMLxInstructions()
DThumb1RegisterInfo.cpp241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); in emitThumbRegPlusImmediate() local
243 AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg) in emitThumbRegPlusImmediate()
291 const MCInstrDesc &MCID = TII.get(ExtraOpc); in emitThumbRegPlusImmediate() local
292 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)) in emitThumbRegPlusImmediate()
360 const MCInstrDesc &MCID = TII.get(ARM::tRSB); in emitThumbConstant() local
361 AddDefaultPred(AddDefaultT1CC(BuildMI(MBB, MBBI, dl, MCID, DestReg)) in emitThumbConstant()
DThumb2ITBlockPass.cpp140 const MCInstrDesc &MCID = MI->getDesc(); in MoveCopyOutOfITBlock() local
142 MI->getOperand(MCID.getNumOperands() - 1).getReg() == ARM::CPSR) in MoveCopyOutOfITBlock()
/external/llvm/lib/Target/
DTargetInstrInfo.cpp34 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass() argument
37 if (OpNum >= MCID.getNumOperands()) in getRegClass()
40 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass()
41 if (MCID.OpInfo[OpNum].isLookupPtrRegClass()) in getRegClass()
/external/llvm/lib/CodeGen/
DScoreboardHazardRecognizer.cpp128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType() local
129 if (MCID == NULL) { in getHazardType()
133 unsigned idx = MCID->getSchedClass(); in getHazardType()
184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
185 assert(MCID && "The scheduler must filter non-machineinstrs"); in EmitInstruction()
186 if (DAG->TII->isZeroCost(MCID->Opcode)) in EmitInstruction()
193 unsigned idx = MCID->getSchedClass(); in EmitInstruction()
DMachineInstr.cpp522 : MCID(0), Flags(0), AsmPrinterFlags(0), in MachineInstr()
530 if (MCID->ImplicitDefs) in addImplicitDefUseOperands()
531 for (const uint16_t *ImpDefs = MCID->getImplicitDefs(); *ImpDefs; ++ImpDefs) in addImplicitDefUseOperands()
533 if (MCID->ImplicitUses) in addImplicitDefUseOperands()
534 for (const uint16_t *ImpUses = MCID->getImplicitUses(); *ImpUses; ++ImpUses) in addImplicitDefUseOperands()
542 : MCID(&tid), Flags(0), AsmPrinterFlags(0), in MachineInstr()
546 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); in MachineInstr()
547 Operands.reserve(NumImplicitOps + MCID->getNumOperands()); in MachineInstr()
557 : MCID(&tid), Flags(0), AsmPrinterFlags(0), in MachineInstr()
561 NumImplicitOps = MCID->getNumImplicitDefs() + MCID->getNumImplicitUses(); in MachineInstr()
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DTargetInstrInfoImpl.cpp63 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction() local
64 bool HasDef = MCID.getNumDefs(); in commuteInstruction()
128 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices() local
129 if (!MCID.isCommutable()) in findCommutedOpIndices()
133 SrcOpIdx1 = MCID.getNumDefs(); in findCommutedOpIndices()
163 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction() local
168 if (MCID.OpInfo[i].isPredicate()) { in PredicateInstruction()
DMachineVerifier.cpp745 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineInstrBefore() local
746 if (MI->getNumOperands() < MCID.getNumOperands()) { in visitMachineInstrBefore()
748 *OS << MCID.getNumOperands() << " operands expected, but " in visitMachineInstrBefore()
789 const MCInstrDesc &MCID = MI->getDesc(); in visitMachineOperand() local
792 if (MONum < MCID.getNumDefs()) { in visitMachineOperand()
793 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; in visitMachineOperand()
800 } else if (MONum < MCID.getNumOperands()) { in visitMachineOperand()
801 const MCOperandInfo &MCOI = MCID.OpInfo[MONum]; in visitMachineOperand()
805 !(MI->isVariadic() && MONum == MCID.getNumOperands()-1)) { in visitMachineOperand()
812 int TiedTo = MCID.getOperandConstraint(MONum, MCOI::TIED_TO); in visitMachineOperand()
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DPeepholeOptimizer.cpp415 const MCInstrDesc &MCID = MI->getDesc(); in isLoadFoldable() local
416 if (MCID.getNumDefs() != 1) in isLoadFoldable()
435 const MCInstrDesc &MCID = MI->getDesc(); in isMoveImmediate() local
438 if (MCID.getNumDefs() != 1) in isMoveImmediate()
DRegAllocFast.cpp850 const MCInstrDesc &MCID = MI->getDesc(); in AllocateBasicBlock() local
964 MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1; in AllocateBasicBlock()
994 (hasTiedOps && (hasPhysDefs || MCID.getNumDefs() > 1))) { in AllocateBasicBlock()
1049 SkippedInstrs.insert(&MCID); in AllocateBasicBlock()
/external/llvm/lib/Target/PowerPC/
DPPCHazardRecognizers.cpp27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction() local
28 if (!MCID) in EmitInstruction()
94 const MCInstrDesc &MCID = TII.get(Opcode); in GetInstrType() local
96 isLoad = MCID.mayLoad(); in GetInstrType()
97 isStore = MCID.mayStore(); in GetInstrType()
99 uint64_t TSFlags = MCID.TSFlags; in GetInstrType()
DPPCInstrInfo.cpp433 const MCInstrDesc &MCID = get(Opc); in copyPhysReg() local
434 if (MCID.getNumOperands() == 3) in copyPhysReg()
435 BuildMI(MBB, I, DL, MCID, DestReg) in copyPhysReg()
438 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/external/llvm/lib/CodeGen/SelectionDAG/
DScheduleDAGFast.cpp252 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
253 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in CopyAndMoveSuccessors()
254 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
259 if (MCID.isCommutable()) in CopyAndMoveSuccessors()
425 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
426 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
427 unsigned NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
428 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
503 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
504 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
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DScheduleDAGRRList.cpp982 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in CopyAndMoveSuccessors() local
983 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in CopyAndMoveSuccessors()
984 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in CopyAndMoveSuccessors()
989 if (MCID.isCommutable()) in CopyAndMoveSuccessors()
1169 const MCInstrDesc &MCID = TII->get(N->getMachineOpcode()); in getPhysicalRegisterVT() local
1170 assert(MCID.ImplicitDefs && "Physical reg def must be in implicit def list!"); in getPhysicalRegisterVT()
1171 unsigned NumRes = MCID.getNumDefs(); in getPhysicalRegisterVT()
1172 for (const uint16_t *ImpDef = MCID.getImplicitDefs(); *ImpDef; ++ImpDef) { in getPhysicalRegisterVT()
1295 const MCInstrDesc &MCID = TII->get(Node->getMachineOpcode()); in DelayForLiveRegsBottomUp() local
1296 if (!MCID.ImplicitDefs) in DelayForLiveRegsBottomUp()
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DInstrEmitter.cpp305 const MCInstrDesc &MCID = MI->getDesc(); in AddRegisterOperand() local
306 bool isOptDef = IIOpNum < MCID.getNumOperands() && in AddRegisterOperand()
307 MCID.OpInfo[IIOpNum].isOptionalDef(); in AddRegisterOperand()
317 assert((DstRC || (MI->isVariadic() && IIOpNum >= MCID.getNumOperands())) && in AddRegisterOperand()
807 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); in EmitMachineNode() local
808 UsedRegs.append(MCID.getImplicitUses(), in EmitMachineNode()
809 MCID.getImplicitUses() + MCID.getNumImplicitUses()); in EmitMachineNode()
DScheduleDAGSDNodes.cpp299 const MCInstrDesc &MCID = TII->get(Opc); in ClusterNodes() local
300 if (MCID.mayLoad()) in ClusterNodes()
434 const MCInstrDesc &MCID = TII->get(Opc); in AddSchedEdges() local
435 for (unsigned i = 0; i != MCID.getNumOperands(); ++i) { in AddSchedEdges()
436 if (MCID.getOperandConstraint(i, MCOI::TIED_TO) != -1) { in AddSchedEdges()
441 if (MCID.isCommutable()) in AddSchedEdges()
/external/llvm/lib/Target/X86/
DX86InstrBuilder.h152 const MCInstrDesc &MCID = MI->getDesc(); variable
154 if (MCID.mayLoad())
156 if (MCID.mayStore())
/external/llvm/lib/Target/Mips/
DMipsDelaySlotFiller.cpp239 MCInstrDesc MCID = MI->getDesc(); in insertDefsUses() local
240 unsigned e = MI->isCall() || MI->isReturn() ? MCID.getNumOperands() : in insertDefsUses()
DMipsInstrInfo.cpp177 const MCInstrDesc &MCID = get(Opc); in BuildCondBr() local
178 MachineInstrBuilder MIB = BuildMI(&MBB, DL, MCID); in BuildCondBr()

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