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Searched refs:PRE_INC (Results 1 – 9 of 9) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DISDOpcodes.h685 PRE_INC, enumerator
/external/llvm/lib/Target/ARM/
DARMISelDAGToDAG.cpp723 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetReg()
759 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImmPre()
779 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode2OffsetImm()
852 ARM_AM::AddrOpc AddSub = (AM == ISD::PRE_INC || AM == ISD::POST_INC) in SelectAddrMode3Offset()
1256 OffImm = ((AM == ISD::PRE_INC) || (AM == ISD::POST_INC)) in SelectT2AddrModeImm8Offset()
1330 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in SelectARMIndexedLoad()
1404 bool isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC); in SelectT2IndexedLoad()
DARMISelLowering.cpp585 for (unsigned im = (unsigned)ISD::PRE_INC; in ARMTargetLowering()
9418 AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC; in getPreIndexedAddressParts()
/external/llvm/lib/Target/PowerPC/
DPPCISelLowering.cpp94 setIndexedLoadAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
95 setIndexedLoadAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
96 setIndexedLoadAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
97 setIndexedLoadAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
98 setIndexedLoadAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
99 setIndexedStoreAction(ISD::PRE_INC, MVT::i1, Legal); in PPCTargetLowering()
100 setIndexedStoreAction(ISD::PRE_INC, MVT::i8, Legal); in PPCTargetLowering()
101 setIndexedStoreAction(ISD::PRE_INC, MVT::i16, Legal); in PPCTargetLowering()
102 setIndexedStoreAction(ISD::PRE_INC, MVT::i32, Legal); in PPCTargetLowering()
103 setIndexedStoreAction(ISD::PRE_INC, MVT::i64, Legal); in PPCTargetLowering()
[all …]
DPPCISelDAGToDAG.cpp898 if (LD->getAddressingMode() != ISD::PRE_INC) in Select()
/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp322 case ISD::PRE_INC: return "<pre-inc>"; in getIndexedModeName()
DTargetLowering.cpp529 for (unsigned IM = (unsigned)ISD::PRE_INC; in TargetLowering()
DDAGCombiner.cpp6773 if (!TLI.isIndexedLoadLegal(ISD::PRE_INC, VT) && in CombineToPreIndexedLoadStore()
6781 if (!TLI.isIndexedStoreLegal(ISD::PRE_INC, VT) && in CombineToPreIndexedLoadStore()
/external/llvm/include/llvm/Target/
DTargetSelectionDAG.td762 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;
772 return AM == ISD::PRE_INC || AM == ISD::PRE_DEC;