Searched refs:SLLV (Results 1 – 8 of 8) sorted by relevance
| /external/v8/src/mips/ |
| D | constants-mips.cc | 246 case SLLV: in InstructionType()
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| D | constants-mips.h | 307 SLLV = ((0 << 3) + 4), enumerator
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| D | disasm-mips.cc | 649 case SLLV: in DecodeTypeRegister()
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| D | simulator-mips.cc | 1762 case SLLV: in ConfigureTypeRegister()
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| D | assembler-mips.cc | 1294 GenInstrRegister(SPECIAL, rs, rt, rd, 0, SLLV); in sllv()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.td | 282 // Format: SLLV ry, rx MIPS16e
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| D | MipsISelLowering.cpp | 1200 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) in EmitAtomicBinaryPartword()
1203 BuildMI(BB, dl, TII->get(Mips::SLLV), Incr2).addReg(ShiftAmt).addReg(Incr); in EmitAtomicBinaryPartword()
1443 BuildMI(BB, dl, TII->get(Mips::SLLV), Mask) in EmitAtomicCmpSwapPartword()
1448 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedCmpVal) in EmitAtomicCmpSwapPartword()
1452 BuildMI(BB, dl, TII->get(Mips::SLLV), ShiftedNewVal) in EmitAtomicCmpSwapPartword()
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| D | MipsInstrInfo.td | 946 def SLLV : shift_rotate_reg<0x04, 0x00, "sllv", shl, CPURegs>;
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