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Searched refs:SrcReg (Results 1 – 25 of 67) sorted by relevance

123

/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp38 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
41 NVPTX::Int32RegsRegClass.contains(SrcReg)) in copyPhysReg()
43 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
45 NVPTX::Int8RegsRegClass.contains(SrcReg)) in copyPhysReg()
47 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
49 NVPTX::Int1RegsRegClass.contains(SrcReg)) in copyPhysReg()
51 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
53 NVPTX::Float32RegsRegClass.contains(SrcReg)) in copyPhysReg()
55 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
57 NVPTX::Int16RegsRegClass.contains(SrcReg)) in copyPhysReg()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp87 unsigned &SrcReg, unsigned &DstReg, in isCoalescableExtInstr() argument
93 SrcReg = MI.getOperand(1).getReg(); in isCoalescableExtInstr()
415 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
418 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
420 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
422 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
424 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
426 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
428 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
436 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
[all …]
DPPCInstrInfo.h72 unsigned SrcReg, bool isKill, int FrameIdx,
96 unsigned &SrcReg, unsigned &DstReg,
123 unsigned DestReg, unsigned SrcReg,
128 unsigned SrcReg, bool isKill, int FrameIndex,
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp87 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
92 if (Mips::CPURegsRegClass.contains(SrcReg)) in copyPhysReg()
94 else if (Mips::CCRRegClass.contains(SrcReg)) in copyPhysReg()
96 else if (Mips::FGR32RegClass.contains(SrcReg)) in copyPhysReg()
98 else if (SrcReg == Mips::HI) in copyPhysReg()
99 Opc = Mips::MFHI, SrcReg = 0; in copyPhysReg()
100 else if (SrcReg == Mips::LO) in copyPhysReg()
101 Opc = Mips::MFLO, SrcReg = 0; in copyPhysReg()
103 else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg. in copyPhysReg()
113 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
[all …]
DMips16InstrInfo.cpp59 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
64 if (Mips::CPURegsRegClass.contains(SrcReg)) in copyPhysReg()
78 if (SrcReg) in copyPhysReg()
79 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
84 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
DMips16InstrInfo.h48 unsigned DestReg, unsigned SrcReg,
53 unsigned SrcReg, bool isKill, int FrameIndex,
/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp43 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
46 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg()
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
53 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
57 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && in storeRegToStackSlot()
58 isARMLowRegister(SrcReg))) && "Unknown regclass!"); in storeRegToStackSlot()
61 (TargetRegisterInfo::isPhysicalRegister(SrcReg) && in storeRegToStackSlot()
62 isARMLowRegister(SrcReg))) { in storeRegToStackSlot()
74 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
DARMBaseInstrInfo.cpp648 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
651 bool GPRSrc = ARM::GPRRegClass.contains(SrcReg); in copyPhysReg()
655 .addReg(SrcReg, getKillRegState(KillSrc)))); in copyPhysReg()
660 bool SPRSrc = ARM::SPRRegClass.contains(SrcReg); in copyPhysReg()
669 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
671 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
676 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
678 MIB.addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
689 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
691 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
[all …]
DThumb1InstrInfo.h44 unsigned DestReg, unsigned SrcReg,
48 unsigned SrcReg, bool isKill, int FrameIndex,
DARMFastISel.cpp184 bool ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr,
190 unsigned ARMEmitIntExt(EVT SrcVT, unsigned SrcReg, EVT DestVT, bool isZExt);
194 unsigned ARMMoveToFPReg(EVT VT, unsigned SrcReg);
195 unsigned ARMMoveToIntReg(EVT VT, unsigned SrcReg);
488 unsigned ARMFastISel::ARMMoveToFPReg(EVT VT, unsigned SrcReg) { in ARMMoveToFPReg() argument
494 .addReg(SrcReg)); in ARMMoveToFPReg()
498 unsigned ARMFastISel::ARMMoveToIntReg(EVT VT, unsigned SrcReg) { in ARMMoveToIntReg() argument
504 .addReg(SrcReg)); in ARMMoveToIntReg()
1114 bool ARMFastISel::ARMEmitStore(EVT VT, unsigned SrcReg, Address &Addr, in ARMEmitStore() argument
1128 .addReg(SrcReg).addImm(1)); in ARMEmitStore()
[all …]
DThumb2InstrInfo.h45 unsigned DestReg, unsigned SrcReg,
50 unsigned SrcReg, bool isKill, int FrameIndex,
/external/llvm/lib/CodeGen/
DStrongPHIElimination.cpp249 unsigned SrcReg = SrcMO.getReg(); in runOnMachineFunction() local
250 addReg(SrcReg); in runOnMachineFunction()
251 unionRegs(DestReg, SrcReg); in runOnMachineFunction()
253 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); in runOnMachineFunction()
291 unsigned SrcReg = BBI->getOperand(i).getReg(); in runOnMachineFunction() local
292 addReg(SrcReg); in runOnMachineFunction()
293 unionRegs(DestReg, SrcReg); in runOnMachineFunction()
308 unsigned SrcReg = PHI->getOperand(1).getReg(); in runOnMachineFunction() local
309 unsigned SrcColor = getRegColor(SrcReg); in runOnMachineFunction()
312 NewReg = SrcReg; in runOnMachineFunction()
[all …]
DTwoAddressInstructionPass.cpp333 unsigned &SrcReg, unsigned &DstReg, in isCopyToReg() argument
335 SrcReg = 0; in isCopyToReg()
339 SrcReg = MI.getOperand(1).getReg(); in isCopyToReg()
342 SrcReg = MI.getOperand(2).getReg(); in isCopyToReg()
346 IsSrcPhys = TargetRegisterInfo::isPhysicalRegister(SrcReg); in isCopyToReg()
382 unsigned SrcReg, DstReg; in isKilled() local
385 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled()
387 Reg = SrcReg; in isKilled()
424 unsigned SrcReg; in findOnlyInterestingUse() local
426 if (isCopyToReg(UseMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) { in findOnlyInterestingUse()
[all …]
DPHIElimination.cpp295 unsigned SrcReg = MPhi->getOperand(i*2+1).getReg(); in LowerAtomicPHINode() local
298 isImplicitlyDefined(SrcReg, MRI); in LowerAtomicPHINode()
299 assert(TargetRegisterInfo::isVirtualRegister(SrcReg) && in LowerAtomicPHINode()
315 findPHICopyInsertPoint(&opBlock, &MBB, SrcReg); in LowerAtomicPHINode()
327 if (MachineInstr *DefMI = MRI->getVRegDef(SrcReg)) in LowerAtomicPHINode()
333 .addReg(SrcReg, 0, SrcSubReg); in LowerAtomicPHINode()
352 bool ValueIsUsed = VRegPHIUseCount[BBVRegPair(opBlock.getNumber(), SrcReg)]; in LowerAtomicPHINode()
356 if (!ValueIsUsed && !LV->isLiveOut(SrcReg, opBlock)) { in LowerAtomicPHINode()
366 if (Term->readsRegister(SrcReg)) in LowerAtomicPHINode()
380 if (KillInst->readsRegister(SrcReg)) in LowerAtomicPHINode()
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DRegisterCoalescer.h36 unsigned SrcReg; variable
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), in CoalescerPair()
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), in CoalescerPair()
105 unsigned getSrcReg() const { return SrcReg; } in getSrcReg()
DPeepholeOptimizer.cpp144 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
145 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
149 TargetRegisterInfo::isPhysicalRegister(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
152 if (MRI->hasOneNonDBGUse(SrcReg)) in INITIALIZE_PASS_DEPENDENCY()
169 getSubClassWithSubReg(MRI->getRegClass(SrcReg), SubIdx) != 0; in INITIALIZE_PASS_DEPENDENCY()
187 UI = MRI->use_nodbg_begin(SrcReg), UE = MRI->use_nodbg_end(); in INITIALIZE_PASS_DEPENDENCY()
263 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg); in INITIALIZE_PASS_DEPENDENCY()
375 unsigned SrcReg, SrcReg2; in optimizeCmpInstr() local
377 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) || in optimizeCmpInstr()
378 TargetRegisterInfo::isPhysicalRegister(SrcReg) || in optimizeCmpInstr()
[all …]
DOptimizePHIs.cpp99 unsigned SrcReg = MI->getOperand(i).getReg(); in IsSingleValuePHICycle() local
100 if (SrcReg == DstReg) in IsSingleValuePHICycle()
102 MachineInstr *SrcMI = MRI->getVRegDef(SrcReg); in IsSingleValuePHICycle()
120 SingleValReg = SrcReg; in IsSingleValuePHICycle()
DPHIEliminationUtils.cpp23 unsigned SrcReg) { in findPHICopyInsertPoint() argument
37 for (MachineRegisterInfo::reg_iterator RI = MRI.reg_begin(SrcReg), in findPHICopyInsertPoint()
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp134 unsigned SrcReg = Src.getReg(); in runOnMachineFunction() local
137 TargetRegisterInfo::isVirtualRegister(SrcReg)) { in runOnMachineFunction()
141 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
158 unsigned SrcReg = Src1.getReg(); in runOnMachineFunction() local
160 std::make_pair(*&SrcReg, 1/*Hexagon::subreg_hireg*/); in runOnMachineFunction()
170 unsigned SrcReg = Src.getReg(); in runOnMachineFunction() local
173 TargetRegisterInfo::isVirtualRegister(SrcReg)) { in runOnMachineFunction()
177 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
193 unsigned SrcReg = Src.getReg(); in runOnMachineFunction() local
195 TargetRegisterInfo::isVirtualRegister(SrcReg)) { in runOnMachineFunction()
[all …]
DHexagonExpandPredSpillCode.cpp84 int SrcReg = MI->getOperand(2).getReg(); in runOnMachineFunction() local
85 assert(Hexagon::PredRegsRegClass.contains(SrcReg) && in runOnMachineFunction()
96 HEXAGON_RESERVED_REG_2).addReg(SrcReg); in runOnMachineFunction()
105 HEXAGON_RESERVED_REG_2).addReg(SrcReg); in runOnMachineFunction()
114 HEXAGON_RESERVED_REG_2).addReg(SrcReg); in runOnMachineFunction()
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp282 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
284 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
286 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
287 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
289 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
290 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
292 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
299 unsigned SrcReg, bool isKill, int FI, in storeRegToStackSlot() argument
308 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot()
311 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp36 unsigned SrcReg, bool isKill, int FrameIdx, in storeRegToStackSlot() argument
53 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
57 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot()
90 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
101 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp336 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
339 bool GRSrc = XCore::GRRegsRegClass.contains(SrcReg); in copyPhysReg()
343 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg()
348 if (GRDest && SrcReg == XCore::SP) { in copyPhysReg()
355 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
363 unsigned SrcReg, bool isKill, in storeRegToStackSlot() argument
371 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
/external/llvm/lib/CodeGen/SelectionDAG/
DInstrEmitter.cpp85 unsigned SrcReg, DenseMap<SDValue, unsigned> &VRBaseMap) { in EmitCopyFromReg() argument
87 if (TargetRegisterInfo::isVirtualRegister(SrcReg)) { in EmitCopyFromReg()
92 bool isNew = VRBaseMap.insert(std::make_pair(Op, SrcReg)).second; in EmitCopyFromReg()
120 } else if (DestReg != SrcReg) in EmitCopyFromReg()
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT); in EmitCopyFromReg()
172 VRBase = SrcReg; in EmitCopyFromReg()
177 VRBase).addReg(SrcReg); in EmitCopyFromReg()
485 unsigned SrcReg, DstReg, DefSubIdx; in EmitSubregNode() local
487 TII->isCoalescableExtInstr(*DefMI, SrcReg, DstReg, DefSubIdx) && in EmitSubregNode()
489 TRC == MRI->getRegClass(SrcReg)) { in EmitSubregNode()
[all …]
/external/llvm/lib/Target/X86/
DX86InstrInfo.h168 unsigned &SrcReg, unsigned &DstReg,
232 unsigned DestReg, unsigned SrcReg,
236 unsigned SrcReg, bool isKill, int FrameIndex,
240 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
379 virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
386 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,

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