| /external/valgrind/main/memcheck/tests/ |
| D | origin1-yes.stderr.exp | 2 Undef 1 of 8 (stack, 32 bit)
9 Undef 2 of 8 (stack, 32 bit)
16 Undef 3 of 8 (stack, 64 bit)
23 Undef 4 of 8 (mallocd, 32-bit)
31 Undef 5 of 8 (realloc)
39 Undef 6 of 8 (MALLOCLIKE_BLOCK)
46 Undef 7 of 8 (brk)
50 Undef 8 of 8 (MAKE_MEM_UNDEFINED)
|
| D | origin3-no.stderr.exp | 2 Undef 1 of 8 (8 bit undef)
12 Undef 2 of 8 (8 bits of 32 undef)
20 Undef 3 of 8 (32 bit undef)
30 Undef 4 of 8 (32 bit undef, unaligned)
40 Undef 5 of 8 (32 bit undef, modified)
50 Undef 6 of 8 (32 bit undef, unaligned, strange, #1)
59 Undef 7 of 8 (32 bit undef, unaligned, strange, #2)
68 Undef 8 of 8 (32 bit undef, unaligned, strange, #3)
|
| D | origin2-not-quite.stderr.exp | 2 Undef 1 of 3 (64-bit FP)
12 Undef 2 of 3 (32-bit FP)
22 Undef 3 of 3 (int)
|
| /external/clang/test/SemaCXX/ |
| D | qualified-id-lookup.cpp | 100 struct Undef { // expected-note{{definition of 'Undef' is not complete until the closing '}'}} struct
103 Undef::type member; argument
105 …static int size = sizeof(Undef); // expected-error{{invalid application of 'sizeof' to an incomple… argument
110 int Undef::f() { in f()
111 return sizeof(Undef); in f()
|
| /external/llvm/unittests/VMCore/ |
| D | ConstantsTest.cpp | 24 Constant* Undef = UndefValue::get(Int1); in TEST() local
52 EXPECT_EQ(Undef, ConstantExpr::getShl(One, One)); in TEST()
60 EXPECT_EQ(Undef, ConstantExpr::getLShr(One, One)); in TEST()
64 EXPECT_EQ(Undef, ConstantExpr::getAShr(One, One)); in TEST()
|
| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 34 Undef = 0x20, enumerator
38 DefineNoRead = Define | Undef,
68 flags & RegState::Undef,
319 return B ? RegState::Undef : 0; in getUndefRegState()
|
| /external/llvm/test/Other/ |
| D | lint.ll | 20 ; CHECK: Undef pointer dereference
22 ; CHECK: Undef pointer dereference
147 ; CHECK: Undefined behavior: Undef pointer dereference
|
| /external/llvm/lib/Transforms/InstCombine/ |
| D | InstCombinePHI.cpp | 786 Value *Undef = UndefValue::get(FirstPhi.getType()); in SliceUpIllegalIntegerPHI() local
788 ReplaceInstUsesWith(*PHIsToSlice[i], Undef); in SliceUpIllegalIntegerPHI()
789 return ReplaceInstUsesWith(FirstPhi, Undef); in SliceUpIllegalIntegerPHI()
|
| D | InstCombineSimplifyDemanded.cpp | 840 Constant *Undef = UndefValue::get(EltTy); in SimplifyDemandedVectorElts() local
845 Elts.push_back(Undef); in SimplifyDemandedVectorElts()
854 Elts.push_back(Undef); in SimplifyDemandedVectorElts()
|
| /external/valgrind/main/coregrind/m_debuginfo/ |
| D | priv_storage.h | 311 } Undef; member
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vuzp.ll | 77 ; Undef shuffle indices should not prevent matching to VUZP:
|
| D | vzip.ll | 77 ; Undef shuffle indices should not prevent matching to VZIP:
|
| D | vtrn.ll | 99 ; Undef shuffle indices should not prevent matching to VTRN:
|
| D | vext.ll | 57 ; Undef shuffle indices should not prevent matching to VEXT:
|
| D | vrev.ll | 115 ; Undef shuffle indices should not prevent matching to VREV:
|
| /external/llvm/lib/Transforms/Scalar/ |
| D | Reassociate.cpp | 762 Constant *Undef = UndefValue::get(I->getType()); in RewriteExprTree() local
764 Undef, Undef, "", I); in RewriteExprTree()
|
| /external/clang/lib/CodeGen/ |
| D | CodeGenFunction.cpp | 366 llvm::Value *Undef = llvm::UndefValue::get(Int32Ty); in StartFunction() local
367 AllocaInsertPt = new llvm::BitCastInst(Undef, Int32Ty, "", EntryBB); in StartFunction()
|
| D | ItaniumCXXABI.cpp | 793 RValue Undef = RValue::get(llvm::UndefValue::get(T)); in EmitReturnFromThunk() local
794 return ItaniumCXXABI::EmitReturnFromThunk(CGF, Undef, ResultType); in EmitReturnFromThunk()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1619 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, in SelectAtomicLoadAdd() local
1627 SDValue RetVals[] = { Undef, Ret }; in SelectAtomicLoadAdd()
1633 SDValue RetVals[] = { Undef, Ret }; in SelectAtomicLoadAdd()
1781 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, in SelectAtomicLoadArith() local
1788 SDValue RetVals[] = { Undef, Ret }; in SelectAtomicLoadArith()
|
| D | X86InstrInfo.cpp | 3477 MachineInstrBuilder(MI).addReg(Reg, RegState::Undef) in Expand2AddrUndef()
3478 .addReg(Reg, RegState::Undef); in Expand2AddrUndef()
3777 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef); in breakPartialRegDependency()
3783 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef) in breakPartialRegDependency()
|
| D | X86ISelLowering.cpp | 13547 SDValue Undef = DAG.getUNDEF(VT); in PerformTruncateCombine() local
13548 OpLo = DAG.getVectorShuffle(VT, dl, OpLo, Undef, ShufMask1); in PerformTruncateCombine()
13549 OpHi = DAG.getVectorShuffle(VT, dl, OpHi, Undef, ShufMask1); in PerformTruncateCombine()
13607 SDValue Undef = DAG.getUNDEF(MVT::v16i8); in PerformTruncateCombine() local
13608 OpLo = DAG.getVectorShuffle(MVT::v16i8, dl, OpLo, Undef, ShufMask1); in PerformTruncateCombine()
13609 OpHi = DAG.getVectorShuffle(MVT::v16i8, dl, OpHi, Undef, ShufMask1); in PerformTruncateCombine()
15682 SDValue Undef = DAG.getUNDEF(OpVT); in PerformSExtCombine() local
15688 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask1[0]); in PerformSExtCombine()
15694 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, Undef, &ShufMask2[0]); in PerformSExtCombine()
|
| /external/llvm/test/Transforms/JumpThreading/ |
| D | basic.ll | 63 ; Undef handling.
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAG.cpp | 4329 SDValue Undef = getUNDEF(Ptr.getValueType()); in getLoad() local
4330 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef, in getLoad()
4340 SDValue Undef = getUNDEF(Ptr.getValueType()); in getExtLoad() local
4341 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef, in getExtLoad()
4392 SDValue Undef = getUNDEF(Ptr.getValueType()); in getStore() local
4393 SDValue Ops[] = { Chain, Val, Ptr, Undef }; in getStore()
4460 SDValue Undef = getUNDEF(Ptr.getValueType()); in getTruncStore() local
4461 SDValue Ops[] = { Chain, Val, Ptr, Undef }; in getTruncStore()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 2125 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); in LowerLOAD() local
2135 SDValue LDL = CreateLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef, in LowerLOAD()
2141 SDValue LWL = CreateLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef, in LowerLOAD()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.cpp | 3447 .addReg(DReg, RegState::Undef) in setExecutionDomain()
|