| /external/llvm/lib/CodeGen/ |
| D | LiveRegMatrix.cpp | 72 void LiveRegMatrix::assign(LiveInterval &VirtReg, unsigned PhysReg) { in assign() argument
73 DEBUG(dbgs() << "assigning " << PrintReg(VirtReg.reg, TRI) in assign()
75 assert(!VRM->hasPhys(VirtReg.reg) && "Duplicate VirtReg assignment"); in assign()
76 VRM->assignVirt2Phys(VirtReg.reg, PhysReg); in assign()
80 Matrix[*Units].unify(VirtReg); in assign()
86 void LiveRegMatrix::unassign(LiveInterval &VirtReg) { in unassign() argument
87 unsigned PhysReg = VRM->getPhys(VirtReg.reg); in unassign()
88 DEBUG(dbgs() << "unassigning " << PrintReg(VirtReg.reg, TRI) in unassign()
90 VRM->clearVirt(VirtReg.reg); in unassign()
93 Matrix[*Units].extract(VirtReg); in unassign()
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| D | LiveIntervalUnion.cpp | 30 void LiveIntervalUnion::unify(LiveInterval &VirtReg) { in unify() argument
31 if (VirtReg.empty()) in unify()
36 LiveInterval::iterator RegPos = VirtReg.begin(); in unify()
37 LiveInterval::iterator RegEnd = VirtReg.end(); in unify()
41 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
51 SegPos.insert(RegEnd->start, RegEnd->end, &VirtReg); in unify()
53 SegPos.insert(RegPos->start, RegPos->end, &VirtReg); in unify()
57 void LiveIntervalUnion::extract(LiveInterval &VirtReg) { in extract() argument
58 if (VirtReg.empty()) in extract()
63 LiveInterval::iterator RegPos = VirtReg.begin(); in extract()
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| D | RegAllocBase.cpp | 84 while (LiveInterval *VirtReg = dequeue()) { in allocatePhysRegs() local
85 assert(!VRM->hasPhys(VirtReg->reg) && "Register already assigned"); in allocatePhysRegs()
88 if (MRI->reg_nodbg_empty(VirtReg->reg)) { in allocatePhysRegs()
89 DEBUG(dbgs() << "Dropping unused " << *VirtReg << '\n'); in allocatePhysRegs()
90 LIS->removeInterval(VirtReg->reg); in allocatePhysRegs()
101 << MRI->getRegClass(VirtReg->reg)->getName() in allocatePhysRegs()
102 << ':' << PrintReg(VirtReg->reg) << ' ' << *VirtReg << '\n'); in allocatePhysRegs()
105 unsigned AvailablePhysReg = selectOrSplit(*VirtReg, SplitVRegs); in allocatePhysRegs()
112 for (MachineRegisterInfo::reg_iterator I = MRI->reg_begin(VirtReg->reg); in allocatePhysRegs()
121 VRM->assignVirt2Phys(VirtReg->reg, in allocatePhysRegs()
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| D | RegAllocFast.cpp | 72 unsigned VirtReg; // Virtual register number. member
78 : LastUse(0), VirtReg(v), PhysReg(0), LastOpNum(0), Dirty(false) {} in LiveReg()
81 return TargetRegisterInfo::virtReg2Index(VirtReg); in getSparseSetIndex()
150 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
155 void killVirtReg(unsigned VirtReg);
157 void spillVirtReg(MachineBasicBlock::iterator MI, unsigned VirtReg);
163 LiveRegMap::iterator findLiveVirtReg(unsigned VirtReg) { in findLiveVirtReg() argument
164 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg()
166 LiveRegMap::const_iterator findLiveVirtReg(unsigned VirtReg) const { in findLiveVirtReg()
167 return LiveVirtRegs.find(TargetRegisterInfo::virtReg2Index(VirtReg)); in findLiveVirtReg()
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| D | RegAllocBasic.cpp | 105 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
114 bool spillInterferences(LiveInterval &VirtReg, unsigned PhysReg,
169 bool RABasic::spillInterferences(LiveInterval &VirtReg, unsigned PhysReg, in spillInterferences() argument
177 LiveIntervalUnion::Query &Q = Matrix->query(VirtReg, *Units); in spillInterferences()
183 if (!Intf->isSpillable() || Intf->weight > VirtReg.weight) in spillInterferences()
189 " interferences with " << VirtReg << "\n"); in spillInterferences()
223 unsigned RABasic::selectOrSplit(LiveInterval &VirtReg, in selectOrSplit() argument
229 AllocationOrder Order(VirtReg.reg, *VRM, RegClassInfo); in selectOrSplit()
232 switch (Matrix->checkInterference(VirtReg, PhysReg)) { in selectOrSplit()
251 if (!spillInterferences(VirtReg, *PhysRegI, SplitVRegs)) in selectOrSplit()
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| D | RegAllocGreedy.cpp | 137 LiveRangeStage getStage(const LiveInterval &VirtReg) const { in getStage()
138 return ExtraRegInfo[VirtReg.reg].Stage; in getStage()
141 void setStage(const LiveInterval &VirtReg, LiveRangeStage Stage) { in setStage() argument
143 ExtraRegInfo[VirtReg.reg].Stage = Stage; in setStage()
354 bool RAGreedy::LRE_CanEraseVirtReg(unsigned VirtReg) { in LRE_CanEraseVirtReg() argument
355 if (VRM->hasPhys(VirtReg)) { in LRE_CanEraseVirtReg()
356 Matrix->unassign(LIS->getInterval(VirtReg)); in LRE_CanEraseVirtReg()
364 void RAGreedy::LRE_WillShrinkVirtReg(unsigned VirtReg) { in LRE_WillShrinkVirtReg() argument
365 if (!VRM->hasPhys(VirtReg)) in LRE_WillShrinkVirtReg()
369 LiveInterval &LI = LIS->getInterval(VirtReg); in LRE_WillShrinkVirtReg()
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| D | LiveIntervalUnion.h | 88 void unify(LiveInterval &VirtReg);
91 void extract(LiveInterval &VirtReg);
108 LiveInterval *VirtReg; variable
118 Query(): LiveUnion(), VirtReg(), Tag(0), UserTag(0) {} in Query()
121 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false), in Query()
127 VirtReg = NULL; in clear()
138 if (UserTag == UTag && VirtReg == VReg && in init()
145 VirtReg = VReg; in init()
151 assert(VirtReg && "uninitialized"); in virtReg()
152 return *VirtReg; in virtReg()
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| D | LiveRegMatrix.h | 106 InterferenceKind checkInterference(LiveInterval &VirtReg, unsigned PhysReg);
111 void assign(LiveInterval &VirtReg, unsigned PhysReg);
116 void unassign(LiveInterval &VirtReg);
128 bool checkRegMaskInterference(LiveInterval &VirtReg, unsigned PhysReg = 0);
133 bool checkRegUnitInterference(LiveInterval &VirtReg, unsigned PhysReg);
139 LiveIntervalUnion::Query &query(LiveInterval &VirtReg, unsigned RegUnit);
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| D | VirtRegMap.h | 133 bool hasPreferredPhys(unsigned VirtReg) { in hasPreferredPhys() argument
134 return getPhys(VirtReg) == getRegAllocPref(VirtReg); in hasPreferredPhys()
151 unsigned getOriginal(unsigned VirtReg) const { in getOriginal() argument
152 unsigned Orig = getPreSplitReg(VirtReg); in getOriginal()
153 return Orig ? Orig : VirtReg; in getOriginal()
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| D | AllocationOrder.cpp | 25 AllocationOrder::AllocationOrder(unsigned VirtReg, in AllocationOrder() argument
29 const TargetRegisterClass *RC = VRM.getRegInfo().getRegClass(VirtReg); in AllocationOrder()
31 VRM.getRegInfo().getRegAllocationHint(VirtReg); in AllocationOrder()
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| D | VirtRegMap.cpp | 228 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(Idx); in addMBBLiveIns() local
229 if (MRI->reg_nodbg_empty(VirtReg)) in addMBBLiveIns()
231 LiveInterval &LI = LIS->getInterval(VirtReg); in addMBBLiveIns()
236 unsigned PhysReg = VRM->getPhys(VirtReg); in addMBBLiveIns()
278 unsigned VirtReg = MO.getReg(); in rewrite() local
279 unsigned PhysReg = VRM->getPhys(VirtReg); in rewrite()
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| D | RegisterCoalescer.h | 68 CoalescerPair(unsigned VirtReg, unsigned PhysReg, in CoalescerPair() argument
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), in CoalescerPair()
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| D | LiveDebugVariables.cpp | 304 UserValue *lookupVirtReg(unsigned VirtReg);
335 void mapVirtReg(unsigned VirtReg, UserValue *EC);
429 void LDVImpl::mapVirtReg(unsigned VirtReg, UserValue *EC) { in mapVirtReg() argument
430 assert(TargetRegisterInfo::isVirtualRegister(VirtReg) && "Only map VirtRegs"); in mapVirtReg()
431 UserValue *&Leader = virtRegToEqClass[VirtReg]; in mapVirtReg()
435 UserValue *LDVImpl::lookupVirtReg(unsigned VirtReg) { in lookupVirtReg() argument
436 if (UserValue *UV = virtRegToEqClass.lookup(VirtReg)) in lookupVirtReg()
903 unsigned VirtReg = Loc.getReg(); in rewriteLocations() local
904 if (VRM.isAssignedReg(VirtReg) && in rewriteLocations()
905 TargetRegisterInfo::isPhysicalRegister(VRM.getPhys(VirtReg))) { in rewriteLocations()
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| D | AllocationOrder.h | 38 AllocationOrder(unsigned VirtReg,
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| D | RegAllocBase.h | 92 virtual unsigned selectOrSplit(LiveInterval &VirtReg,
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| D | InlineSpiller.cpp | 833 bool InlineSpiller::reMaterializeFor(LiveInterval &VirtReg, in reMaterializeFor() argument
836 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); in reMaterializeFor()
842 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) in reMaterializeFor()
858 markValueUsed(&VirtReg, ParentVNI); in reMaterializeFor()
867 MIBundleOperands(MI).analyzeVirtReg(VirtReg.reg, &Ops); in reMaterializeFor()
869 markValueUsed(&VirtReg, ParentVNI); in reMaterializeFor()
896 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) { in reMaterializeFor()
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| D | PHIElimination.cpp | 176 static bool isImplicitlyDefined(unsigned VirtReg, in isImplicitlyDefined() argument
178 for (MachineRegisterInfo::def_iterator DI = MRI->def_begin(VirtReg), in isImplicitlyDefined()
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| D | PrologEpilogInserter.cpp | 821 unsigned VirtReg = 0; in scavengeFrameVirtualRegs() local
841 if (Reg != VirtReg) { in scavengeFrameVirtualRegs()
847 VirtReg = Reg; in scavengeFrameVirtualRegs()
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| D | MachineTraceMetrics.cpp | 529 DataDep(const MachineRegisterInfo *MRI, unsigned VirtReg, unsigned UseOp) in DataDep()
531 assert(TargetRegisterInfo::isVirtualRegister(VirtReg)); in DataDep()
532 MachineRegisterInfo::def_iterator DefI = MRI->def_begin(VirtReg); in DataDep()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ScheduleDAGInstrs.h | 101 unsigned VirtReg; member
104 VReg2SUnit(unsigned reg, SUnit *su): VirtReg(reg), SU(su) {} in VReg2SUnit()
107 return TargetRegisterInfo::virtReg2Index(VirtReg); in getSparseSetIndex()
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| /external/llvm/docs/ |
| D | CodeGenerator.rst | 1235 unsigned VirtReg = TargetRegisterInfo::index2VirtReg(i);
1236 stuff(VirtReg);
2142 OperandTy: VirtReg, | VirtReg, UnsImm, VirtReg, SignExtImm PhysReg
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