Searched refs:getRegClassFor (Results 1 – 13 of 13) sorted by relevance
99 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()137 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()337 && TLI->getRegClassFor(VT) in rawRegPressureDelta()338 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()348 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()349 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()491 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()502 const TargetRegisterClass *RC = TLI->getRegClassFor(VT); in scheduledNode()
106 UseRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()166 DstRC = TLI->getRegClassFor(VT); in EmitCopyFromReg()275 const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getValueType()); in getVR()445 RC = TRI->getSubClassWithSubReg(TLI->getRegClassFor(VT), SubIdx); in ConstrainForSubReg()481 const TargetRegisterClass *TRC = TLI->getRegClassFor(Node->getValueType(0)); in EmitSubregNode()536 const TargetRegisterClass *SRC = TLI->getRegClassFor(Node->getValueType(0)); in EmitSubregNode()
214 Reg = createResultReg(TLI.getRegClassFor(VT)); in materializeRegForValue()759 const TargetRegisterClass* SrcClass = TLI.getRegClassFor(SrcVT); in SelectBitCast()760 const TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT); in SelectBitCast()1386 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in FastEmitInst_extractsubreg()
212 return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT)); in CreateReg()
6221 (RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT))); in visitInlineAsm()6759 unsigned SRetReg = RegInfo.createVirtualRegister(TLI.getRegClassFor(RegVT)); in LowerArguments()
476 unsigned ResultReg = createResultReg(TLI.getRegClassFor(RetVT)); in FastEmitInst_extractsubreg()491 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToFPReg()501 unsigned MoveReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMoveToIntReg()527 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()544 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeFP()565 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32)); in ARMMaterializeInt()579 unsigned ImmReg = createResultReg(TLI.getRegClassFor(MVT::i32)); in ARMMaterializeInt()591 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeInt()621 unsigned DestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()679 unsigned NewDestReg = createResultReg(TLI.getRegClassFor(VT)); in ARMMaterializeGV()[all …]
361 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const;
1026 const TargetRegisterClass *ARMTargetLowering::getRegClassFor(EVT VT) const { in getRegClassFor() function in ARMTargetLowering1036 return TargetLowering::getRegClassFor(VT); in getRegClassFor()3330 unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32)); in LowerRETURNADDR()
1043 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in EmitAtomicBinary()1131 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in EmitAtomicBinaryPartword()1283 const TargetRegisterClass *RC = getRegClassFor(MVT::getIntegerVT(Size * 8)); in EmitAtomicCmpSwap()1366 const TargetRegisterClass *RC = getRegClassFor(MVT::i32); in EmitAtomicCmpSwapPartword()2000 unsigned Reg = MF.addLiveIn(RA, getRegClassFor(VT)); in LowerRETURNADDR()3105 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i32)); in LowerFormalArguments()
222 virtual const TargetRegisterClass *getRegClassFor(EVT VT) const { in getRegClassFor() function
974 unsigned Reg = MF.addLiveIn(TRI->getRARegister(), getRegClassFor(MVT::i32)); in LowerRETURNADDR()
2133 const TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy()); in TargetMaterializeAlloca()
1954 Reg = MF.getRegInfo().createVirtualRegister(getRegClassFor(MVT::i64)); in LowerFormalArguments()9438 getRegClassFor(Subtarget->is64Bit() ? MVT::i64:MVT::i32); in LowerDYNAMIC_STACKALLOC()12293 const TargetRegisterClass *AddrRegClass = getRegClassFor(MVT::i64); in EmitVAARG64WithCustomInserter()12294 const TargetRegisterClass *OffsetRegClass = getRegClassFor(MVT::i32); in EmitVAARG64WithCustomInserter()12726 getRegClassFor(Is64Bit ? MVT::i64:MVT::i32); in EmitLoweredSegAlloca()