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Searched refs:isTypeLegal (Results 1 – 23 of 23) sorted by relevance

/external/llvm/lib/CodeGen/SelectionDAG/
DResourcePriorityQueue.cpp98 if (TLI->isTypeLegal(VT) in numberRCValPredInSU()
136 if (TLI->isTypeLegal(VT) in numberRCValSuccInSU()
336 if (TLI->isTypeLegal(VT) in rawRegPressureDelta()
348 if (TLI->isTypeLegal(VT) && TLI->getRegClassFor(VT) in rawRegPressureDelta()
490 if (TLI->isTypeLegal(VT)) { in scheduledNode()
501 if (TLI->isTypeLegal(VT)) { in scheduledNode()
DFastISel.cpp132 if (!TLI.isTypeLegal(VT)) { in getRegForValue()
350 if (!TLI.isTypeLegal(VT)) { in SelectBinaryOp()
704 if (!TLI.isTypeLegal(DstVT)) in SelectCast()
708 if (!TLI.isTypeLegal(SrcVT)) in SelectCast()
745 !TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT)) in SelectBitCast()
874 if (!TLI.isTypeLegal(IntVT)) in SelectFNeg()
910 if (!TLI.isTypeLegal(VT) && VT != MVT::i1) in SelectExtractValue()
1444 if (VT == MVT::Other || !TLI.isTypeLegal(VT)) { in HandlePHINodesInSuccessorBlocks()
DTargetLowering.cpp633 assert(isTypeLegal(VT)); in canOpTrap()
667 while (NumElts > 1 && !TLI->isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) { in getVectorTypeBreakdownMVT()
675 if (!TLI->isTypeLegal(NewVT)) in getVectorTypeBreakdownMVT()
700 if (isTypeLegal(*I)) in isLegalRC()
771 if (isTypeLegal(IVT)) { in computeRegisterProperties()
781 if (!isTypeLegal(MVT::ppcf128)) { in computeRegisterProperties()
790 if (!isTypeLegal(MVT::f64)) { in computeRegisterProperties()
799 if (!isTypeLegal(MVT::f32)) { in computeRegisterProperties()
800 if (isTypeLegal(MVT::f64)) { in computeRegisterProperties()
817 if (isTypeLegal(VT)) continue; in computeRegisterProperties()
[all …]
DLegalizeTypesGeneric.cpp99 if (isTypeLegal(NVT)) { in ExpandRes_BITCAST()
291 if (isTypeLegal(NVT)) { in ExpandOp_BITCAST()
424 assert(isTypeLegal(Ptr.getValueType()) && "Pointers must be legal!"); in ExpandOp_NormalStore()
DLegalizeTypes.cpp129 } else if (isTypeLegal(Res.getValueType()) || IgnoreNodeResults(I)) { in PerformExpensiveChecks()
409 if (!isTypeLegal(I->getValueType(i))) { in run()
417 !isTypeLegal(I->getOperand(i).getValueType())) { in run()
DLegalizeDAG.cpp311 if (TLI.isTypeLegal(intVT)) { in ExpandUnalignedStore()
431 if (TLI.isTypeLegal(intVT) && TLI.isTypeLegal(LoadedVT)) { in ExpandUnalignedLoad()
654 TLI.isTypeLegal(MVT::i32)) { in OptimizeFloatStore()
664 if (TLI.isTypeLegal(MVT::i64)) { in OptimizeFloatStore()
671 if (TLI.isTypeLegal(MVT::i32) && !ST->isVolatile()) { in OptimizeFloatStore()
843 assert(TLI.isTypeLegal(StVT) && in LegalizeStoreOps()
1073 if (!TLI.isLoadExtLegal(ISD::EXTLOAD, SrcVT) && TLI.isTypeLegal(SrcVT)) { in LegalizeLoadOps()
1490 if (TLI.isTypeLegal(IVT)) { in ExpandFCOPYSIGN()
2045 if (Op0.getValueType() == MVT::i32 && TLI.isTypeLegal(MVT::f64)) { in ExpandLegalINT_TO_FP()
2850 if (!TLI.isTypeLegal(EltVT)) { in ExpandNode()
[all …]
DLegalizeVectorTypes.cpp1397 while (!TLI.isTypeLegal(VT) && NumElts != 1) { in WidenVecRes_Binary()
1441 } while (!TLI.isTypeLegal(VT) && NumElts != 1); in WidenVecRes_Binary()
1478 } while (!TLI.isTypeLegal(NextVT)); in WidenVecRes_Binary()
1551 if (TLI.isTypeLegal(InWidenVT)) { in WidenVecRes_Convert()
1710 if (TLI.isTypeLegal(NewInVT)) { in WidenVecRes_BITCAST()
1850 if (TLI.isTypeLegal(InWidenVT)) { in WidenVecRes_CONVERT_RNDSAT()
2173 if (TLI.isTypeLegal(NewVT)) { in WidenVecOp_BITCAST()
2297 if (TLI.isTypeLegal(MemVT) && (WidenWidth % MemVTWidth) == 0 && in FindMemType()
2312 if (TLI.isTypeLegal(MemVT) && WidenEltVT == MemVT.getVectorElementType() && in FindMemType()
DDAGCombiner.cpp321 bool isTypeLegal(const EVT &VT) { in isTypeLegal() function in __anon16627d380111::DAGCombiner
323 return TLI.isTypeLegal(VT); in isTypeLegal()
2315 TLI.isTypeLegal(Op0VT))) && in SimplifyBinOpWithSameOpcodeHands()
3170 if (!TLI.isTypeLegal(VT)) return 0; in MatchRotate()
5281 if (isa<ConstantSDNode>(EltNo) && isTypeLegal(NVT)) { in visitTRUNCATE()
5466 if (isTypeLegal(IntXVT)) { in visitBITCAST()
6352 if (N0CFP && isTypeLegal(EVT)) { in visitFP_ROUND_INREG()
7233 if (!DC->isTypeLegal(VT)) in ShrinkLoadReplaceStoreWithStore()
7489 if ((isTypeLegal(MVT::i32) && !LegalOperations && !ST->isVolatile()) || in visitSTORE()
7499 if ((TLI.isTypeLegal(MVT::i64) && !LegalOperations && in visitSTORE()
[all …]
DInstrEmitter.cpp105 if (TLI->isTypeLegal(VT)) in EmitCopyFromReg()
DLegalizeTypes.h72 bool isTypeLegal(EVT VT) const { in isTypeLegal() function
DSelectionDAGBuilder.cpp299 TLI.isTypeLegal(ValueVT)) in getCopyFromPartsVector()
339 assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!"); in getCopyToParts()
606 if (!TLI.isTypeLegal(RegisterVT)) in areValueTypesLegal()
1723 if (!TLI.isTypeLegal(VT)) in visitBitTestHeader()
5559 if (!TLI.isTypeLegal(LoadVT) ||!TLI.allowsUnalignedMemoryAccesses(LoadVT)) in visitMemCmpCall()
DLegalizeIntegerTypes.cpp517 if (!TLI.isTypeLegal(SVT)) in PromoteIntRes_SETCC()
2082 if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) || in ExpandIntRes_Shift()
DSelectionDAG.cpp3464 while (!TLI.isTypeLegal(LVT)) in FindOptimalMemOpLowering()
3479 while (!TLI.isTypeLegal(VT)) in FindOptimalMemOpLowering()
/external/llvm/lib/Target/X86/
DX86FastISel.cpp140 bool isTypeLegal(Type *Ty, MVT &VT, bool AllowI1 = false);
150 bool X86FastISel::isTypeLegal(Type *Ty, MVT &VT, bool AllowI1) { in isTypeLegal() function in X86FastISel
170 return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT); in isTypeLegal()
699 if (!isTypeLegal(I->getOperand(0)->getType(), VT, /*AllowI1=*/true)) in X86SelectStore()
825 if (!isTypeLegal(I->getType(), VT, /*AllowI1=*/true)) in X86SelectLoad()
914 if (!isTypeLegal(I->getOperand(0)->getType(), VT)) in X86SelectCmp()
994 if (!TLI.isTypeLegal(DstVT)) in X86SelectZExt()
1102 isTypeLegal(TI->getOperand(0)->getType(), SourceVT)) { in X86SelectBranch()
1191 if (!isTypeLegal(I->getType(), VT)) in X86SelectShift()
1218 if (!isTypeLegal(I->getType(), VT)) in X86SelectSelect()
[all …]
DX86ISelLowering.cpp4990 DAG.getTargetLoweringInfo().isTypeLegal(MVT::v2i64)) { in EltsFromConsecutiveLoads()
11222 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) { in LowerATOMIC_STORE()
11240 if (!DAG.getTargetLoweringInfo().isTypeLegal(VT)) in LowerADDC_ADDE_SUBC_SUBE()
13478 if (!DCI.isBeforeLegalize() && !TLI.isTypeLegal(VT.getVectorElementType())) in PerformShuffleCombine()
13824 VT != MVT::f80 && DAG.getTargetLoweringInfo().isTypeLegal(VT) && in PerformSELECTCombine()
13968 if (DAG.getTargetLoweringInfo().isTypeLegal(LHS.getValueType())) { in PerformSELECTCombine()
14607 if (!DAG.getTargetLoweringInfo().isTypeLegal(EltVT) && in PerformShiftCombine()
15105 if (TLI.isTypeLegal(Tp) && ((MemSz % Tp.getSizeInBits()) == 0)) { in PerformLOADCombine()
15111 if (TLI.isTypeLegal(MVT::f64) && SclrLoadTy.getSizeInBits() < 64 && in PerformLOADCombine()
15133 if (!TLI.isTypeLegal(WideVecVT)) in PerformLOADCombine()
[all …]
/external/llvm/include/llvm/Target/
DTargetLowering.h250 bool isTypeLegal(EVT VT) const { in isTypeLegal() function
401 return (VT == MVT::Other || isTypeLegal(VT)) && in isOperationLegalOrCustom()
409 return (VT == MVT::Other || isTypeLegal(VT)) && in isOperationLegal()
445 return isTypeLegal(ValVT) && MemVT.isSimple() && in isTruncStoreLegal()
533 } while (!isTypeLegal(NVT) || in getTypeToPromoteTo()
971 return isTypeLegal(VT); in isTypeDesirableForOp()
/external/llvm/lib/CodeGen/
DAnalysis.cpp234 TLI.isTypeLegal(EVT::getEVT(Op->getType())) && in getNoopInput()
235 TLI.isTypeLegal(EVT::getEVT(I->getType()))) in getNoopInput()
/external/llvm/lib/Target/ARM/
DARMFastISel.cpp177 bool isTypeLegal(Type *Ty, MVT &VT);
755 bool ARMFastISel::isTypeLegal(Type *Ty, MVT &VT) { in isTypeLegal() function in ARMFastISel
764 return TLI.isTypeLegal(VT); in isTypeLegal()
768 if (isTypeLegal(Ty, VT)) return true; in isLoadTypeLegal()
1567 if (!isTypeLegal(Ty, DstVT)) in SelectIToFP()
1610 if (!isTypeLegal(RetTy, DstVT)) in SelectFPToI()
1639 if (!isTypeLegal(I->getType(), VT)) in SelectSelect()
1700 if (!isTypeLegal(Ty, VT)) in SelectDiv()
1728 if (!isTypeLegal(Ty, VT)) in SelectRem()
2168 else if (!isTypeLegal(RetTy, RetVT)) in ARMEmitLibcall()
[all …]
DARMISelLowering.cpp3369 if (SrcVT == MVT::i64 && TLI.isTypeLegal(DstVT)) { in ExpandBITCAST()
3379 if (DstVT == MVT::i64 && TLI.isTypeLegal(SrcVT)) { in ExpandBITCAST()
7579 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformANDCombine()
7622 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformORCombine()
7662 DAG.getTargetLoweringInfo().isTypeLegal(VT)) { in PerformORCombine()
7809 if(!DAG.getTargetLoweringInfo().isTypeLegal(VT)) in PerformXORCombine()
7948 if (!TLI.isTypeLegal(WideVecVT)) return SDValue(); in PerformSTORECombine()
7961 if (TLI.isTypeLegal(Tp) && Tp.getSizeInBits() <= NumElems * ToEltSz) in PerformSTORECombine()
7965 if (!TLI.isTypeLegal(StoreType)) in PerformSTORECombine()
8146 if (!TLI.isTypeLegal(VT) || in PerformVECTOR_SHUFFLECombine()
[all …]
/external/llvm/lib/Transforms/Scalar/
DCodeGenPrepare.cpp1063 TLI && (TLI->isTypeLegal(TLI->getValueType(LI->getType())) || in MoveExtToFormExtLoad()
1064 !TLI->isTypeLegal(TLI->getValueType(I->getType()))) && in MoveExtToFormExtLoad()
DLoopStrengthReduce.cpp1694 if (!TLI->isTypeLegal(DVT)) continue; in OptimizeShadowIV()
/external/llvm/lib/Target/NVPTX/
DNVPTXISelLowering.cpp1128 if (isTypeLegal(VT)) in isTypeSupportedInIntrinsic()
1132 if (isTypeLegal(eVT)) in isTypeSupportedInIntrinsic()
/external/llvm/lib/Target/CellSPU/
DSPUISelLowering.cpp414 if (!isTypeLegal(VT)) continue; in SPUTargetLowering()