| /external/llvm/lib/Target/Sparc/ |
| D | DelaySlotFiller.cpp | 223 if (MO.isUse()) { in delayHasHazard()
245 assert(Reg.isUse() && "JMPL first operand is not a use."); in insertCallUses()
252 assert(RegOrImm.isUse() && "JMPLrr second operand is not a use."); in insertCallUses()
273 if (MO.isUse()) in insertDefsUses()
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| /external/llvm/lib/CodeGen/ |
| D | ProcessImplicitDefs.cpp | 71 if (MO->isReg() && MO->isUse() && MO->readsReg()) in canTurnIntoImplicitDef()
114 if (MO->isUse()) in processImplicitDef()
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| D | MachineInstr.cpp | 300 if (isUndef() && isUse()) { in print()
732 if (Operands[OpNo].isUse()) { in addOperand()
1021 if (getOperand(OpIdx).isUse() && isRegTiedToDefOperand(OpIdx, &DefIdx)) in getRegClassConstraint()
1062 if (!MO.isReg() || !MO.isUse()) in findRegisterUseOperandIdx()
1094 if (MO.isUse()) in readsWritesVirtualRegister()
1174 assert(UseMO.isUse() && "UseIdx must be a use operand"); in tieOperands()
1206 if (MO.isUse()) in findTiedOperandIdx()
1211 if (UseMO.isReg() && UseMO.isUse() && UseMO.TiedTo == OpIdx + 1) in findTiedOperandIdx()
1255 if (MO.isReg() && MO.isUse()) in clearKillInfo()
1370 if (MO.isUse()) in isSafeToReMat()
[all …]
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| D | Spiller.cpp | 113 hasUse |= mi->getOperand(i).isUse(); in trivialSpillEverywhere()
127 if (mop.isUse() && !mi->isRegTiedToDefOperand(mopIdx)) { in trivialSpillEverywhere()
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| D | ExpandPostRAPseudos.cpp | 89 if (!MO.isReg() || !MO.isImplicit() || MO.isUse()) in TransferImplicitDefs()
99 (MI->getOperand(2).isReg() && MI->getOperand(2).isUse()) && in LowerSubregToReg()
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| D | RegAllocFast.cpp | 220 if (MO.isUse() && !LR.LastUse->isRegTiedToDefOperand(LR.LastOpNum)) { in addKillFlag()
592 if (LRI->LastUse != MI || LRI->LastUse->getOperand(LRI->LastOpNum).isUse()) in defineVirtReg()
624 if (MO.isUse()) in reloadVirtReg()
724 if (MO.isUse()) { in handleThroughOperands()
806 if (!MO.isReg() || !MO.isUse()) in addRetOperands()
962 if (MO.isUse()) { in AllocateBasicBlock()
974 if (MO.isUse()) { in AllocateBasicBlock()
1010 if (MO.isUse()) { in AllocateBasicBlock()
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| D | TwoAddressInstructionPass.cpp | 209 if (MO.isUse() && MOReg != SavedReg) in Sink3AddrInstruction()
320 if (MO.isUse() && DI->second < LastUse) in NoUseAfterLastDef()
399 if (!MO.isReg() || !MO.isUse() || MO.getReg() != Reg) in isTwoAddrUse()
918 if (MO.isUse()) { in RescheduleKillAboveMI()
958 if (MO.isUse()) { in RescheduleKillAboveMI()
1156 if (MO.isUse()) { in TryInstructionTransform()
1220 assert(SrcReg && SrcMO.isUse() && "two address instruction invalid"); in collectTiedOperands()
1300 assert(MO.isReg() && MO.getReg() == RegB && MO.isUse() && in processTiedPairs()
1324 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
1348 if (MO.isReg() && MO.getReg() == RegB && MO.isUse()) { in processTiedPairs()
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| D | CriticalAntiDepBreaker.cpp | 218 if (MO.isUse() && Special) { in PrescanInstruction()
284 if (!MO.isUse()) continue; in ScanInstruction()
583 if (MO.isUse() && TRI->regsOverlap(AntiDepReg, Reg)) { in BreakAntiDependencies()
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| D | RegisterScavenging.cpp | 158 if (MO.isUse()) { in forward()
182 if (MO.isUse()) { in forward()
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| D | MachineCSE.cpp | 122 if (!MO.isReg() || !MO.isUse()) in INITIALIZE_PASS_DEPENDENCY()
178 if (MO.isUse()) in isPhysDefTriviallyDead()
367 if (MO.isReg() && MO.isUse() && in isProfitableToCSE()
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| D | TargetInstrInfoImpl.cpp | 358 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!"); in foldMemoryOperand()
430 if (MO.isUse()) { in isReallyTriviallyReMaterializableGeneric()
451 if (MO.isUse()) in isReallyTriviallyReMaterializableGeneric()
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| D | DeadMachineInstructionElim.cpp | 186 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
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| D | MachineSink.cpp | 493 if (MO.isUse()) { in FindSuccToSinkTo()
505 if (MO.isUse()) continue; in FindSuccToSinkTo()
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| D | BranchFolding.cpp | 154 if (!MO.isReg() || !MO.isUse()) in OptimizeImpDefsBlock()
1492 if (MO.isUse()) { in findHoistingInsertPosAndDeps()
1519 if (!MO.isReg() || MO.isUse()) in findHoistingInsertPosAndDeps()
1553 if (MO.isUse()) { in findHoistingInsertPosAndDeps()
1684 if (!MO.isReg() || !MO.isUse() || !MO.isKill()) in HoistCommonCodeInSuccs()
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| D | PostRASchedulerList.cpp | 532 if (!MO.isReg() || !MO.isUse()) continue; in FixupKills()
567 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue; in FixupKills()
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| D | LiveRangeCalc.cpp | 71 if (MO.isUse()) in extendToUses()
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| D | MachineLICM.cpp | 934 if (MO.isUse()) { in IsLoopInvariantInst()
952 if (!MO.isUse()) in IsLoopInvariantInst()
1023 if (!MO.isReg() || !MO.isUse()) in HasHighOperandLatency()
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| D | InlineSpiller.cpp | 842 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) in reMaterializeFor()
896 if (MO.isReg() && MO.isUse() && MO.getReg() == VirtReg.reg) { in reMaterializeFor()
1197 if (MO.isUse()) { in spillAroundUses()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsDelaySlotFiller.cpp | 225 if (MO.isUse()) { in delayHasHazard()
256 else if (MO.isUse()) in insertDefsUses()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonNewValueJump.cpp | 134 (II->getOperand(i).isUse() || II->getOperand(i).isDef())) { in canBeFeederToNewValueJump()
556 if (MO.isReg() && MO.isUse()) { in runOnMachineFunction()
563 if (localMO.isReg() && localMO.isUse() && in runOnMachineFunction()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 485 if ((!ReturnUses && op->isUse()) || in defusechain_iterator()
519 if (Op->isUse())
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| D | MachineOperand.h | 267 bool isUse() const { in isUse() function
326 return !isUndef() && !isInternalRead() && (isUse() || getSubReg()); in readsReg()
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| D | LiveIntervalAnalysis.h | 110 static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
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| D | ScheduleDAGInstrs.h | 79 if (!MO.isReg() || !MO.isUse()) in VisitRegion()
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| /external/llvm/lib/Target/ARM/ |
| D | Thumb2ITBlockPass.cpp | 68 if (MO.isUse()) in TrackDefUses()
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