Home
last modified time | relevance | path

Searched refs:sltu (Results 1 – 21 of 21) sorted by relevance

/external/openssl/crypto/bn/asm/
Dbn-mips.s37 sltu $2,$13,$2 # All manuals say it "compares 32-bit
45 sltu $1,$13,$1
52 sltu $2,$15,$2
58 sltu $1,$15,$1
66 sltu $2,$9,$2
72 sltu $1,$9,$1
79 sltu $2,$11,$2
84 sltu $1,$11,$1
101 sltu $2,$13,$2
106 sltu $1,$13,$1
[all …]
Dmips-mont.s68 sltu $1,$24,$10
86 sltu $1,$10,$11
87 sltu $2,$24,$25
94 sltu $1,$24,$10
99 sltu $2,$22,$9
108 sltu $1,$10,$11
112 sltu $2,$24,$25
115 sltu $1,$24,$10
121 sltu $1,$25,$11
141 sltu $1,$10,$20
[all …]
Dmips3.s89 sltu v0,t1,v0 /* All manuals say it "compares 32-bit
96 sltu AT,t1,AT
104 sltu v0,t3,v0
109 sltu AT,t3,AT
118 sltu v0,ta1,v0
123 sltu AT,ta1,AT
131 sltu v0,ta3,v0
136 sltu AT,ta3,AT
155 sltu v0,t1,v0
160 sltu AT,t1,AT
[all …]
/external/llvm/test/CodeGen/Mips/
D2008-06-05-Carry.ll6 ; CHECK: sltu
17 ; CHECK: sltu
/external/llvm/test/MC/Mips/
Dmips-alu-instructions.s25 # CHECK: sltu $3, $3, $5 # encoding: [0x2b,0x18,0x65,0x00]
52 sltu $3, $3, $5
/external/v8/test/cctest/
Dtest-disasm-mips.cc356 COMPARE(sltu(a0, a1, a2), in TEST()
358 COMPARE(sltu(s0, s1, s2), in TEST()
360 COMPARE(sltu(t2, t3, t4), in TEST()
362 COMPARE(sltu(v0, v1, a2), in TEST()
Dtest-assembler-mips.cc188 __ sltu(v0, t7, t3); in TEST() local
/external/webkit/Source/JavaScriptCore/assembler/
DMacroAssemblerMIPS.h919 m_assembler.sltu(cmpTempRegister, right, left); in branch32()
923 m_assembler.sltu(cmpTempRegister, left, right); in branch32()
927 m_assembler.sltu(cmpTempRegister, left, right); in branch32()
931 m_assembler.sltu(cmpTempRegister, right, left); in branch32()
1376 m_assembler.sltu(dest, MIPSRegisters::zero, dest); in set32Compare32()
1378 m_assembler.sltu(dest, right, left); in set32Compare32()
1380 m_assembler.sltu(dest, left, right); in set32Compare32()
1383 m_assembler.sltu(dest, left, right); in set32Compare32()
1385 m_assembler.sltu(dest, right, left); in set32Compare32()
1434 m_assembler.sltu(dest, MIPSRegisters::zero, dataTempRegister); in set32Test8()
[all …]
DMIPSAssembler.h365 void sltu(RegisterID rd, RegisterID rs, RegisterID rt) in sltu() function
/external/v8/src/mips/
Dmacro-assembler-mips.cc732 sltu(rd, rs, rt.rm()); in Sltu()
740 sltu(rd, rs, at); in Sltu()
1728 sltu(scratch, r2, rs); in BranchShort()
1736 sltu(scratch, rs, r2); in BranchShort()
1745 sltu(scratch, rs, r2); in BranchShort()
1753 sltu(scratch, r2, rs); in BranchShort()
1836 sltu(scratch, r2, rs); in BranchShort()
1849 sltu(scratch, rs, r2); in BranchShort()
1863 sltu(scratch, rs, r2); in BranchShort()
1873 sltu(scratch, r2, rs); in BranchShort()
[all …]
Ddeoptimizer-mips.cc173 patcher.masm()->sltu(at, sp, t0); in RevertStackCheckCodeAt()
Dassembler-mips.h776 void sltu(Register rd, Register rs, Register rt);
Dassembler-mips.cc1556 void Assembler::sltu(Register rd, Register rs, Register rt) { in sltu() function in v8::internal::Assembler
Dfull-codegen-mips.cc380 __ sltu(at, sp, t0); in EmitStackCheck() local
/external/llvm/test/MC/Disassembler/Mips/
Dmips32r2.txt369 # CHECK: sltu $3, $3, $5
Dmips32r2_le.txt369 # CHECK: sltu $3, $3, $5
Dmips32.txt348 # CHECK: sltu $3, $3, $5
Dmips32_le.txt348 # CHECK: sltu $3, $3, $5
/external/llvm/lib/Target/Mips/
DMips64InstrInfo.td99 def SLTu64 : SetCC_R<0x00, 0x2b, "sltu", setult, CPU64Regs>;
DMipsInstrInfo.td936 def SLTu : SetCC_R<0x00, 0x2b, "sltu", setult, CPURegs>;
/external/webkit/Source/JavaScriptCore/
DChangeLog-2010-05-246764 (JSC::MIPSAssembler::sltu):