| /external/llvm/lib/Target/Mips/ |
| D | Mips16ISelDAGToDAG.cpp | 246 case ISD::ADDE: { in selectNode()
249 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectNode()
254 if (Opcode == ISD::ADDE) { in selectNode()
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| D | MipsSEISelDAGToDAG.cpp | 206 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectAddESubE()
323 case ISD::ADDE: { in selectNode()
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| D | MipsISelLowering.cpp | 379 setTargetDAGCombine(ISD::ADDE); in MipsTargetLowering()
853 case ISD::ADDE: in PerformDAGCombine()
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 216 ADDE, SUBE, enumerator
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| D | SelectionDAG.h | 933 case ISD::ADDE: return true;
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| /external/llvm/lib/Target/R600/ |
| D | AMDILISelLowering.cpp | 103 setOperationAction(ISD::ADDE, VT, Expand); in InitAMDILLowering()
201 setOperationAction(ISD::ADDE, MVT::Other, Expand); in InitAMDILLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1395 setOperationAction(ISD::ADDE, MVT::i8, Expand); in HexagonTargetLowering()
1396 setOperationAction(ISD::ADDE, MVT::i16, Expand); in HexagonTargetLowering()
1397 setOperationAction(ISD::ADDE, MVT::i32, Expand); in HexagonTargetLowering()
1398 setOperationAction(ISD::ADDE, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.h | 81 ADDE, // Add using carry enumerator
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| D | ARMISelLowering.cpp | 658 setOperationAction(ISD::ADDE, MVT::i32, Custom); in ARMTargetLowering()
966 case ARMISD::ADDE: return "ARMISD::ADDE"; in getTargetNodeName()
5498 case ISD::ADDE: Opc = ARMISD::ADDE; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
5604 case ISD::ADDE: in LowerOperation()
7736 if (AddeNode->getOpcode() != ISD::ADDE) in AddCombineTo64bitMLAL()
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| D | ARMInstrInfo.td | 154 def ARMadde : SDNode<"ARMISD::ADDE", SDTBinaryArithWithFlagsInOut>;
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| /external/qemu/tcg/ppc/ |
| D | tcg-target.c | 346 #define ADDE XO31(138) macro
1617 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5])); in tcg_out_op()
1622 tcg_out32 (s, ADDE | TAB (args[1], args[3], args[5])); in tcg_out_op()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 201 case ISD::ADDE: return "adde"; in getOperationName()
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| D | LegalizeIntegerTypes.cpp | 1159 case ISD::ADDE: in ExpandIntegerResult()
1297 Hi = DAG.getNode(ISD::ADDE, DL, VTList, HiOps, 3); in ExpandShiftByConstant()
1548 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUB()
1597 Hi = DAG.getNode(ISD::ADDE, dl, VTList, HiOps, 3); in ExpandIntRes_ADDSUBC()
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| D | SelectionDAG.cpp | 2025 case ISD::ADDE: { in ComputeMaskedBits()
3196 case ISD::ADDE: in getNode()
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| D | DAGCombiner.cpp | 1103 case ISD::ADDE: return visitADDE(N); in visit()
1594 return DAG.getNode(ISD::ADDE, N->getDebugLoc(), N->getVTList(), in visitADDE()
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| /external/qemu/tcg/ppc64/ |
| D | tcg-target.c | 336 #define ADDE XO31(138) macro
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 343 def adde : SDNode<"ISD::ADDE" , SDTIntBinOp,
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 90 setOperationAction(ISD::ADDE, MVT::i32, Expand); in XCoreTargetLowering()
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| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 317 case ISD::ADDE: in IsProfitableToFold()
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| D | X86ISelLowering.cpp | 372 setOperationAction(ISD::ADDE, VT, Custom); in X86TargetLowering()
12047 case ISD::ADDE: Opc = X86ISD::ADC; ExtraOp = true; break; in LowerADDC_ADDE_SUBC_SUBE()
12172 case ISD::ADDE: in LowerOperation()
12238 case ISD::ADDE: in ReplaceNodeResults()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCInstrInfo.td | 1353 def ADDE : XOForm_1<31, 138, 0, (outs GPRC:$rT), (ins GPRC:$rA, GPRC:$rB),
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| /external/icu4c/test/testdata/ |
| D | NormalizationTest-3.2.0.txt | 2731 ADDE;ADDE;1100 1172 11A9;ADDE;1100 1172 11A9;
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| /external/icu4c/data/unidata/ |
| D | NormalizationTest.txt | 2886 ADDE;ADDE;1100 1172 11A9;ADDE;1100 1172 11A9;
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| /external/valgrind/main/VEX/orig_x86/ |
| D | manyfp.orig | 4651 . 1452 805ADDE 29
|