Searched refs:ArgRegs (Results 1 – 6 of 6) sorted by relevance
| /external/llvm/lib/Target/ARM/ |
| D | ARMFastISel.cpp | 207 SmallVectorImpl<unsigned> &ArgRegs,
1901 SmallVectorImpl<unsigned> &ArgRegs, in ProcessCallArgs() argument
1967 unsigned Arg = ArgRegs[VA.getValNo()]; in ProcessCallArgs()
2221 SmallVector<unsigned, 8> ArgRegs; in ARMEmitLibcall() local
2225 ArgRegs.reserve(I->getNumOperands()); in ARMEmitLibcall()
2242 ArgRegs.push_back(Arg); in ARMEmitLibcall()
2250 if (!ProcessCallArgs(Args, ArgRegs, ArgVTs, ArgFlags, in ARMEmitLibcall()
2332 SmallVector<unsigned, 8> ArgRegs; in SelectCall() local
2337 ArgRegs.reserve(arg_size); in SelectCall()
2375 ArgRegs.push_back(Arg); in SelectCall()
[all …]
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1178 static const uint16_t ArgRegs[] = { in LowerCCCArguments() local
1182 unsigned FirstVAReg = CCInfo.getFirstUnallocated(ArgRegs, in LowerCCCArguments()
1183 array_lengthof(ArgRegs)); in LowerCCCArguments()
1184 if (FirstVAReg < array_lengthof(ArgRegs)) { in LowerCCCArguments()
1189 for (int i = array_lengthof(ArgRegs) - 1; i >= (int)FirstVAReg; --i) { in LowerCCCArguments()
1199 RegInfo.addLiveIn(ArgRegs[i], VReg); in LowerCCCArguments()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 662 static const uint16_t ArgRegs[] = { in CC_MBlaze_AssignReg() local
667 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_MBlaze_AssignReg()
668 unsigned Reg = State.AllocateReg(ArgRegs, NumArgRegs); in CC_MBlaze_AssignReg()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 301 static const uint16_t ArgRegs[] = { in LowerFormalArguments() local
304 unsigned NumAllocated = CCInfo.getFirstUnallocated(ArgRegs, 6); in LowerFormalArguments()
305 const uint16_t *CurArgReg = ArgRegs+NumAllocated, *ArgRegEnd = ArgRegs+6; in LowerFormalArguments()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 3635 const uint16_t *ArgRegs = CC.intArgRegs(); in passByValArg() local
3647 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; in passByValArg()
3698 unsigned ArgReg = ArgRegs[ByVal.FirstIdx + I]; in passByValArg()
3722 const uint16_t *ArgRegs = CC.intArgRegs(); in writeVarArgRegs() local
3724 unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs, NumRegs); in writeVarArgRegs()
3751 unsigned Reg = addLiveIn(MF, ArgRegs[I], RC); in writeVarArgRegs()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 1773 static const uint16_t ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignArgRegs() local
1777 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
1779 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC32_SVR4_Custom_AlignArgRegs()
1786 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignArgRegs()
1800 static const uint16_t ArgRegs[] = { in CC_PPC32_SVR4_Custom_AlignFPArgRegs() local
1805 const unsigned NumArgRegs = array_lengthof(ArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
1807 unsigned RegNum = State.getFirstUnallocated(ArgRegs, NumArgRegs); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
1811 if (RegNum != NumArgRegs && ArgRegs[RegNum] == PPC::F8) { in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
1812 State.AllocateReg(ArgRegs[RegNum]); in CC_PPC32_SVR4_Custom_AlignFPArgRegs()
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