| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXRegisterInfo.cpp | 106 static const uint16_t CalleeSavedRegs[] = { 0 }; in getCalleeSavedRegs() local
107 return CalleeSavedRegs; in getCalleeSavedRegs()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcRegisterInfo.cpp | 38 static const uint16_t CalleeSavedRegs[] = { 0 }; in getCalleeSavedRegs() local
39 return CalleeSavedRegs; in getCalleeSavedRegs()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMCallingConv.td | 193 def CSR_NoRegs : CalleeSavedRegs<(add)>;
195 def CSR_AAPCS : CalleeSavedRegs<(add LR, R11, R10, R9, R8, R7, R6, R5, R4,
200 def CSR_iOS : CalleeSavedRegs<(add LR, R7, R6, R5, R4, (sub CSR_AAPCS, R9))>;
205 // def CSR_GHC : CalleeSavedRegs<()>;
206 def CSR_GHC : CalleeSavedRegs<(add)>;
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeRegisterInfo.cpp | 60 static const uint16_t CalleeSavedRegs[] = { in getCalleeSavedRegs() local
67 return CalleeSavedRegs; in getCalleeSavedRegs()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCCallingConv.td | 108 def CSR_Darwin32 : CalleeSavedRegs<(add R13, R14, R15, R16, R17, R18, R19, R20,
116 def CSR_SVR432 : CalleeSavedRegs<(add R14, R15, R16, R17, R18, R19, R20, VRSAVE,
124 def CSR_Darwin64 : CalleeSavedRegs<(add X13, X14, X15, X16, X17, X18, X19, X20,
132 def CSR_SVR464 : CalleeSavedRegs<(add X14, X15, X16, X17, X18, X19, X20, VRSAVE,
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| /external/llvm/lib/Target/X86/ |
| D | X86CallingConv.td | 511 def CSR_NoRegs : CalleeSavedRegs<(add)>;
513 def CSR_32 : CalleeSavedRegs<(add ESI, EDI, EBX, EBP)>;
514 def CSR_64 : CalleeSavedRegs<(add RBX, R12, R13, R14, R15, RBP)>;
516 def CSR_32EHRet : CalleeSavedRegs<(add EAX, EDX, CSR_32)>;
517 def CSR_64EHRet : CalleeSavedRegs<(add RAX, RDX, CSR_64)>;
519 def CSR_Win64 : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12, R13, R14, R15,
522 def CSR_MostRegs_64 : CalleeSavedRegs<(add RBX, RCX, RDX, RSI, RDI, R8, R9, R10,
527 def CSR_Win64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add RBX, RBP, RDI, RSI, R12,
532 def CSR_64_Intel_OCL_BI : CalleeSavedRegs<(add CSR_64,
536 def CSR_64_Intel_OCL_BI_AVX : CalleeSavedRegs<(add CSR_64,
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430RegisterInfo.cpp | 45 static const uint16_t CalleeSavedRegs[] = { in getCalleeSavedRegs() local
73 CalleeSavedRegsIntr : CalleeSavedRegs); in getCalleeSavedRegs()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsCallingConv.td | 214 def CSR_SingleFloatOnly : CalleeSavedRegs<(add (sequence "F%u", 31, 20), RA, FP,
217 def CSR_O32 : CalleeSavedRegs<(add (sequence "D%u", 15, 10), RA, FP,
220 def CSR_N32 : CalleeSavedRegs<(add D31_64, D29_64, D27_64, D25_64, D24_64,
224 def CSR_N64 : CalleeSavedRegs<(add (sequence "D%u_64", 31, 24), RA_64, FP_64,
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| /external/llvm/include/llvm/Target/ |
| D | TargetCallingConv.td | 137 /// CalleeSavedRegs - A list of callee saved registers for a given calling
141 /// For each CalleeSavedRegs def, TableGen will emit a FOO_SaveList array for
144 class CalleeSavedRegs<dag saves> {
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreRegisterInfo.cpp | 64 static const uint16_t CalleeSavedRegs[] = { in getCalleeSavedRegs() local
69 return CalleeSavedRegs; in getCalleeSavedRegs()
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| /external/llvm/include/llvm/CodeGen/ |
| D | RegisterScavenging.h | 61 BitVector CalleeSavedRegs; variable
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| /external/llvm/lib/CodeGen/ |
| D | RegisterScavenging.cpp | 92 CalleeSavedRegs.resize(NumPhysRegs); in enterBasicBlock()
96 CalleeSavedRegs.set(CSRegs[i]); in enterBasicBlock()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64CallingConv.td | 187 def CSR_PCS : CalleeSavedRegs<(add (sequence "X%u", 30, 19),
195 def TLSDesc : CalleeSavedRegs<(add (sequence "X%u", 29, 1),
|