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Searched refs:DestReg (Results 1 – 25 of 60) sorted by relevance

123

/external/llvm/lib/Target/Hexagon/
DHexagonSplitTFRCondSets.cpp90 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
106 if (DestReg != SrcReg1) { in runOnMachineFunction()
108 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg1); in runOnMachineFunction()
110 if (DestReg != SrcReg2) { in runOnMachineFunction()
112 DestReg).addReg(MI->getOperand(1).getReg()).addReg(SrcReg2); in runOnMachineFunction()
120 int DestReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
125 if (DestReg != SrcReg1) { in runOnMachineFunction()
127 TII->get(Hexagon::TFR_cPt), DestReg). in runOnMachineFunction()
132 TII->get(Hexagon::TFRI_cNotPt), DestReg). in runOnMachineFunction()
137 TII->get(Hexagon::TFRI_cNotPt_f), DestReg). in runOnMachineFunction()
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCInstrInfo.cpp410 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
413 if (PPC::GPRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
415 else if (PPC::G8RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
417 else if (PPC::F4RCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
419 else if (PPC::CRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
421 else if (PPC::VRRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
423 else if (PPC::CRBITRCRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
430 BuildMI(MBB, I, DL, MCID, DestReg) in copyPhysReg()
433 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg()
573 unsigned DestReg, int FrameIdx, in LoadRegFromStackSlot() argument
[all …]
DPPCInstrInfo.h77 unsigned DestReg, int FrameIdx,
125 unsigned DestReg, unsigned SrcReg,
136 unsigned DestReg, int FrameIndex,
/external/llvm/lib/Target/R600/
DSIInstrInfo.cpp37 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
43 assert(DestReg != AMDGPU::SCC && SrcReg != AMDGPU::SCC); in copyPhysReg()
68 if (AMDGPU::SReg_32RegClass.contains(DestReg)) { in copyPhysReg()
70 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), DestReg) in copyPhysReg()
74 } else if (AMDGPU::SReg_64RegClass.contains(DestReg)) { in copyPhysReg()
76 BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B64), DestReg) in copyPhysReg()
80 } else if (AMDGPU::SReg_128RegClass.contains(DestReg)) { in copyPhysReg()
85 } else if (AMDGPU::SReg_256RegClass.contains(DestReg)) { in copyPhysReg()
90 } else if (AMDGPU::SReg_512RegClass.contains(DestReg)) { in copyPhysReg()
95 } else if (AMDGPU::VReg_32RegClass.contains(DestReg)) { in copyPhysReg()
[all …]
DR600MachineScheduler.cpp229 unsigned DestReg = MI->getOperand(0).getReg(); in getAluKind() local
230 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_XRegClass) || in getAluKind()
231 regBelongsToClass(DestReg, &AMDGPU::R600_AddrRegClass)) in getAluKind()
233 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_YRegClass)) in getAluKind()
235 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_ZRegClass)) in getAluKind()
237 if (regBelongsToClass(DestReg, &AMDGPU::R600_TReg32_WRegClass)) in getAluKind()
239 if (regBelongsToClass(DestReg, &AMDGPU::R600_Reg128RegClass)) in getAluKind()
328 unsigned DestReg = MI->getOperand(0).getReg(); in AssignSlot() local
341 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_XRegClass); in AssignSlot()
344 MRI->constrainRegClass(DestReg, &AMDGPU::R600_TReg32_YRegClass); in AssignSlot()
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXInstrInfo.cpp38 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
40 if (NVPTX::Int32RegsRegClass.contains(DestReg) && in copyPhysReg()
42 BuildMI(MBB, I, DL, get(NVPTX::IMOV32rr), DestReg) in copyPhysReg()
44 else if (NVPTX::Int8RegsRegClass.contains(DestReg) && in copyPhysReg()
46 BuildMI(MBB, I, DL, get(NVPTX::IMOV8rr), DestReg) in copyPhysReg()
48 else if (NVPTX::Int1RegsRegClass.contains(DestReg) && in copyPhysReg()
50 BuildMI(MBB, I, DL, get(NVPTX::IMOV1rr), DestReg) in copyPhysReg()
52 else if (NVPTX::Float32RegsRegClass.contains(DestReg) && in copyPhysReg()
54 BuildMI(MBB, I, DL, get(NVPTX::FMOV32rr), DestReg) in copyPhysReg()
56 else if (NVPTX::Int16RegsRegClass.contains(DestReg) && in copyPhysReg()
[all …]
DNVPTXInstrInfo.h55 unsigned DestReg, unsigned SrcReg,
59 unsigned &DestReg) const;
/external/llvm/lib/Target/ARM/
DThumb1RegisterInfo.cpp68 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool() argument
79 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
93 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmInReg() argument
99 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
110 unsigned LdReg = DestReg; in emitThumbRegPlusImmInReg()
111 if (DestReg == ARM::SP) { in emitThumbRegPlusImmInReg()
131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmInReg()
134 if (DestReg == ARM::SP || isSub) in emitThumbRegPlusImmInReg()
170 unsigned DestReg, unsigned BaseReg, in emitThumbRegPlusImmediate() argument
186 if (DestReg == BaseReg && BaseReg == ARM::SP) { in emitThumbRegPlusImmediate()
[all …]
DThumb1InstrInfo.cpp43 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
45 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
47 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
81 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
85 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
86 isARMLowRegister(DestReg))) && "Unknown regclass!"); in loadRegFromStackSlot()
89 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
90 isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
101 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) in loadRegFromStackSlot()
DThumb2InstrInfo.cpp114 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
118 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
153 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
169 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
174 ARMBaseInstrInfo::loadRegFromStackSlot(MBB, I, DestReg, FI, RC, TRI); in loadRegFromStackSlot()
179 unsigned DestReg, unsigned BaseReg, int NumBytes, in emitT2RegPlusImmediate() argument
187 if (DestReg != ARM::SP && DestReg != BaseReg && in emitT2RegPlusImmediate()
193 BuildMI(MBB, MBBI, dl, TII.get(ARM::t2MOVi16), DestReg) in emitT2RegPlusImmediate()
[all …]
DARMBaseInstrInfo.cpp654 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
656 bool GPRDest = ARM::GPRRegClass.contains(DestReg); in copyPhysReg()
660 AddDefaultCC(AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::MOVr), DestReg) in copyPhysReg()
665 bool SPRDest = ARM::SPRRegClass.contains(DestReg); in copyPhysReg()
675 else if (ARM::DPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
677 else if (ARM::QPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
681 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc), DestReg); in copyPhysReg()
695 if (ARM::QQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
697 else if (ARM::QQQQPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
700 else if (ARM::DPairRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
[all …]
DThumb1InstrInfo.h44 unsigned DestReg, unsigned SrcReg,
54 unsigned DestReg, int FrameIndex,
DThumb2RegisterInfo.cpp38 unsigned DestReg, unsigned SubIdx, in emitLoadConstPool() argument
49 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
DARMBaseInstrInfo.h111 unsigned DestReg, unsigned SrcReg,
122 unsigned DestReg, int FrameIndex,
136 unsigned DestReg, unsigned SubIdx,
384 unsigned DestReg, unsigned BaseReg, int NumBytes,
390 unsigned DestReg, unsigned BaseReg, int NumBytes,
395 unsigned DestReg, unsigned BaseReg,
DThumb2InstrInfo.h45 unsigned DestReg, unsigned SrcReg,
56 unsigned DestReg, int FrameIndex,
/external/llvm/lib/CodeGen/
DStrongPHIElimination.cpp243 unsigned DestReg = BBI->getOperand(0).getReg(); in runOnMachineFunction() local
244 addReg(DestReg); in runOnMachineFunction()
251 unionRegs(DestReg, SrcReg); in runOnMachineFunction()
287 unsigned DestReg = BBI->getOperand(0).getReg(); in runOnMachineFunction() local
288 addReg(DestReg); in runOnMachineFunction()
293 unionRegs(DestReg, SrcReg); in runOnMachineFunction()
317 unsigned DestReg = PHI->getOperand(0).getReg(); in runOnMachineFunction() local
318 if (!InsertedDestCopies.count(DestReg)) in runOnMachineFunction()
319 MergeLIsAndRename(DestReg, NewReg); in runOnMachineFunction()
340 unsigned DestReg = I->first; in runOnMachineFunction() local
[all …]
/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp87 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
91 if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
104 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
106 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
108 else if (DestReg == Mips::HI) in copyPhysReg()
109 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
110 else if (DestReg == Mips::LO) in copyPhysReg()
111 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
113 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
115 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
[all …]
DMips16InstrInfo.cpp70 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
74 if (Mips::CPU16RegsRegClass.contains(DestReg) && in copyPhysReg()
77 else if (Mips::CPURegsRegClass.contains(DestReg) && in copyPhysReg()
81 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
85 (Mips::CPU16RegsRegClass.contains(DestReg))) in copyPhysReg()
93 if (DestReg) in copyPhysReg()
94 MIB.addReg(DestReg, RegState::Define); in copyPhysReg()
118 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
129 BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(0) in loadRegFromStackSlot()
/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp282 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
284 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
285 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
287 else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
288 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
290 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
291 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD), DestReg) in copyPhysReg()
321 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
328 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
330 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0); in loadRegFromStackSlot()
[all …]
/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h235 unsigned DestReg) { in BuildMI() argument
237 .addReg(DestReg, RegState::Define); in BuildMI()
248 unsigned DestReg) { in BuildMI() argument
252 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
259 unsigned DestReg) { in BuildMI() argument
263 return MachineInstrBuilder(MF, MI).addReg(DestReg, RegState::Define); in BuildMI()
270 unsigned DestReg) { in BuildMI() argument
273 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
277 return BuildMI(BB, MII, DL, MCID, DestReg); in BuildMI()
334 unsigned DestReg) { in BuildMI() argument
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp43 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
47 if (DestReg == AArch64::XSP || SrcReg == AArch64::XSP) { in copyPhysReg()
49 BuildMI(MBB, I, DL, get(AArch64::ADDxxi_lsl0_s), DestReg) in copyPhysReg()
53 } else if (DestReg == AArch64::WSP || SrcReg == AArch64::WSP) { in copyPhysReg()
55 BuildMI(MBB, I, DL, get(AArch64::ADDwwi_lsl0_s), DestReg) in copyPhysReg()
59 } else if (DestReg == AArch64::NZCV) { in copyPhysReg()
66 assert(AArch64::GPR64RegClass.contains(DestReg)); in copyPhysReg()
68 BuildMI(MBB, I, DL, get(AArch64::MRSxi), DestReg) in copyPhysReg()
70 } else if (AArch64::GPR64RegClass.contains(DestReg)) { in copyPhysReg()
74 } else if (AArch64::GPR32RegClass.contains(DestReg)) { in copyPhysReg()
[all …]
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp64 unsigned DestReg, int FrameIdx, in loadRegFromStackSlot() argument
80 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
83 .addReg(DestReg).addFrameIndex(FrameIdx).addImm(0).addMemOperand(MMO); in loadRegFromStackSlot()
90 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
93 if (MSP430::GR16RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
95 else if (MSP430::GR8RegClass.contains(DestReg, SrcReg)) in copyPhysReg()
100 BuildMI(MBB, I, DL, get(Opc), DestReg) in copyPhysReg()
DMSP430InstrInfo.h56 unsigned DestReg, unsigned SrcReg,
67 unsigned DestReg, int FrameIdx,
/external/llvm/lib/Target/XCore/
DXCoreInstrInfo.cpp336 unsigned DestReg, unsigned SrcReg, in copyPhysReg() argument
338 bool GRDest = XCore::GRRegsRegClass.contains(DestReg); in copyPhysReg()
342 BuildMI(MBB, I, DL, get(XCore::ADD_2rus), DestReg) in copyPhysReg()
349 BuildMI(MBB, I, DL, get(XCore::LDAWSP_ru6), DestReg).addImm(0); in copyPhysReg()
353 if (DestReg == XCore::SP && GRSrc) { in copyPhysReg()
378 unsigned DestReg, int FrameIndex, in loadRegFromStackSlot() argument
384 BuildMI(MBB, I, DL, get(XCore::LDWFI), DestReg) in loadRegFromStackSlot()
DXCoreInstrInfo.h66 unsigned DestReg, unsigned SrcReg,
77 unsigned DestReg, int FrameIndex,

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