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Searched refs:DstReg (Results 1 – 25 of 50) sorted by relevance

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/external/llvm/lib/Target/R600/
DR600ExpandSpecialInstrs.cpp113 unsigned DstReg; in runOnMachineFunction() local
116 DstReg = MI.getOperand(Chan).getReg(); in runOnMachineFunction()
118 DstReg = Chan == 2 ? AMDGPU::T0_Z : AMDGPU::T0_W; in runOnMachineFunction()
121 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
142 unsigned DstReg; in runOnMachineFunction() local
145 DstReg = Chan == 0 ? AMDGPU::T0_X : AMDGPU::T0_Y; in runOnMachineFunction()
147 DstReg = MI.getOperand(Chan-2).getReg(); in runOnMachineFunction()
150 DstReg, MI.getOperand(3 + (Chan % 2)).getReg(), PReg); in runOnMachineFunction()
170 unsigned DstReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
174 TRI.getSubReg(DstReg, TRI.getSubRegFromChannel(Chan)), PReg); in runOnMachineFunction()
[all …]
DAMDGPUIndirectAddressing.cpp104 unsigned DstReg = MRI.createVirtualRegister(IndirectStoreRegClass); in runOnMachineFunction() local
106 BuildMI(MBB, I, MBB.findDebugLoc(I), TII->get(AMDGPU::COPY), DstReg) in runOnMachineFunction()
109 RegisterAddressMap[DstReg] = Address; in runOnMachineFunction()
110 LiveAddressRegisterMap[Address] = DstReg; in runOnMachineFunction()
119 unsigned DstReg = MRI.createVirtualRegister(IndirectStoreRegClass); in runOnMachineFunction() local
120 MOV.addReg(DstReg, RegState::Define | RegState::Implicit); in runOnMachineFunction()
121 RegisterAddressMap[DstReg] = Addr; in runOnMachineFunction()
122 LiveAddressRegisterMap[Addr] = DstReg; in runOnMachineFunction()
DR600InstrInfo.h63 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
159 unsigned DstReg,
165 unsigned DstReg,
DR600InstrInfo.cpp76 unsigned DstReg, int64_t Imm) const { in getMovImmInstr() argument
79 MIB.addReg(DstReg, RegState::Define); in getMovImmInstr()
652 unsigned DstReg, in buildDefaultInstruction() argument
656 DstReg); // $dst in buildDefaultInstruction()
691 unsigned DstReg, in buildMovImm() argument
693 MachineInstr *MovImm = buildDefaultInstruction(BB, I, AMDGPU::MOV, DstReg, in buildMovImm()
DAMDGPUInstrInfo.h53 unsigned &DstReg, unsigned &SubIdx) const;
141 virtual MachineInstr* getMovImmInstr(MachineFunction *MF, unsigned DstReg,
DSIInstrInfo.cpp151 MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg, in getMovImmInstr() argument
155 MIB.addReg(DstReg, RegState::Define); in getMovImmInstr()
DSIInstrInfo.h41 virtual MachineInstr * getMovImmInstr(MachineFunction *MF, unsigned DstReg,
/external/llvm/lib/Target/Hexagon/
DHexagonPeephole.cpp133 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
136 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
141 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
157 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
159 PeepholeDoubleRegsMap[DstReg] = in runOnMachineFunction()
169 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
172 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
177 PeepholeMap[DstReg] = SrcReg; in runOnMachineFunction()
192 unsigned DstReg = Dst.getReg(); in runOnMachineFunction() local
194 if (TargetRegisterInfo::isVirtualRegister(DstReg) && in runOnMachineFunction()
DHexagonExpandPredSpillCode.cpp124 int DstReg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
125 assert(Hexagon::PredRegsRegClass.contains(DstReg) && in runOnMachineFunction()
146 DstReg).addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
155 DstReg).addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
161 DstReg).addReg(HEXAGON_RESERVED_REG_2); in runOnMachineFunction()
/external/llvm/lib/CodeGen/
DTwoAddressInstructionPass.cpp124 void scanUses(unsigned DstReg);
333 unsigned &SrcReg, unsigned &DstReg, in isCopyToReg() argument
336 DstReg = 0; in isCopyToReg()
338 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
341 DstReg = MI.getOperand(0).getReg(); in isCopyToReg()
347 IsDstPhys = TargetRegisterInfo::isPhysicalRegister(DstReg); in isCopyToReg()
417 unsigned SrcReg, DstReg; in isKilled() local
420 if (!isCopyToReg(*DefMI, TII, SrcReg, DstReg, IsSrcPhys, IsDstPhys)) in isKilled()
428 static bool isTwoAddrUse(MachineInstr &MI, unsigned Reg, unsigned &DstReg) { in isTwoAddrUse() argument
438 DstReg = MI.getOperand(ti).getReg(); in isTwoAddrUse()
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DRegisterCoalescer.h33 unsigned DstReg; variable
63 : TRI(tri), DstReg(0), SrcReg(0), DstIdx(0), SrcIdx(0), in CoalescerPair()
70 : TRI(tri), DstReg(PhysReg), SrcReg(VirtReg), DstIdx(0), SrcIdx(0), in CoalescerPair()
102 unsigned getDstReg() const { return DstReg; } in getDstReg()
DOptimizePHIs.cpp87 unsigned DstReg = MI->getOperand(0).getReg(); in IsSingleValuePHICycle() local
100 if (SrcReg == DstReg) in IsSingleValuePHICycle()
130 unsigned DstReg = MI->getOperand(0).getReg(); in IsDeadPHICycle() local
131 assert(TargetRegisterInfo::isVirtualRegister(DstReg) && in IsDeadPHICycle()
142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(DstReg), in IsDeadPHICycle()
DExpandPostRAPseudos.cpp85 unsigned DstReg = MI->getOperand(0).getReg(); in LowerSubregToReg() local
91 unsigned DstSubReg = TRI->getSubReg(DstReg, SubIdx); in LowerSubregToReg()
93 assert(TargetRegisterInfo::isPhysicalRegister(DstReg) && in LowerSubregToReg()
111 if (DstReg != InsReg) { in LowerSubregToReg()
126 CopyMI->addRegisterDefined(DstReg); in LowerSubregToReg()
DPeepholeOptimizer.cpp150 unsigned SrcReg, DstReg, SubIdx; in INITIALIZE_PASS_DEPENDENCY() local
151 if (!TII->isCoalescableExtInstr(*MI, SrcReg, DstReg, SubIdx)) in INITIALIZE_PASS_DEPENDENCY()
154 if (TargetRegisterInfo::isPhysicalRegister(DstReg) || in INITIALIZE_PASS_DEPENDENCY()
164 const TargetRegisterClass *DstRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
181 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end(); in INITIALIZE_PASS_DEPENDENCY()
264 UI = MRI->use_nodbg_begin(DstReg), UE = MRI->use_nodbg_end(); in INITIALIZE_PASS_DEPENDENCY()
279 MRI->clearKillFlags(DstReg); in INITIALIZE_PASS_DEPENDENCY()
280 MRI->constrainRegClass(DstReg, DstRC); in INITIALIZE_PASS_DEPENDENCY()
286 .addReg(DstReg, 0, SubIdx); in INITIALIZE_PASS_DEPENDENCY()
DRegisterCoalescer.cpp179 void updateRegDefsUses(unsigned SrcReg, unsigned DstReg, unsigned SubIdx);
252 SrcReg = DstReg = 0; in setRegisters()
336 DstReg = Dst; in setRegisters()
341 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) in flip()
343 std::swap(SrcReg, DstReg); in flip()
365 if (TargetRegisterInfo::isPhysicalRegister(DstReg)) { in isCoalescable()
374 return DstReg == Dst; in isCoalescable()
376 return TRI.getSubReg(DstReg, SrcSub) == Dst; in isCoalescable()
379 if (DstReg != Dst) in isCoalescable()
736 unsigned DstReg = CP.isFlipped() ? CP.getSrcReg() : CP.getDstReg(); in reMaterializeTrivialDef() local
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DMachineSink.cpp129 unsigned DstReg = MI->getOperand(0).getReg(); in INITIALIZE_PASS_DEPENDENCY() local
131 !TargetRegisterInfo::isVirtualRegister(DstReg) || in INITIALIZE_PASS_DEPENDENCY()
136 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); in INITIALIZE_PASS_DEPENDENCY()
145 MRI->replaceRegWith(DstReg, SrcReg); in INITIALIZE_PASS_DEPENDENCY()
DEarlyIfConversion.cpp462 unsigned DstReg = PI.PHI->getOperand(0).getReg(); in replacePHIInstrs() local
463 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); in replacePHIInstrs()
483 unsigned DstReg = MRI->createVirtualRegister(MRI->getRegClass(PHIDst)); in rewritePHIOperands() local
484 TII->insertSelect(*Head, FirstTerm, HeadDL, DstReg, Cond, PI.TReg, PI.FReg); in rewritePHIOperands()
492 PI.PHI->getOperand(i-2).setReg(DstReg); in rewritePHIOperands()
/external/llvm/lib/Target/MSP430/
DMSP430RegisterInfo.cpp143 unsigned DstReg = MI.getOperand(0).getReg(); in eliminateFrameIndex() local
145 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::SUB16ri), DstReg) in eliminateFrameIndex()
146 .addReg(DstReg).addImm(-Offset); in eliminateFrameIndex()
148 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg) in eliminateFrameIndex()
149 .addReg(DstReg).addImm(Offset); in eliminateFrameIndex()
DMSP430InstrFormats.td40 def DstReg : DestMode<0>;
98 : IForm8<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
102 : IForm8<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>;
106 : IForm8<opcode, DstReg, SrcMem, Size4Bytes, outs, ins, asmstr, pattern>;
127 : IForm16<opcode, DstReg, SrcReg, Size2Bytes, outs, ins, asmstr, pattern>;
131 : IForm16<opcode, DstReg, SrcImm, Size4Bytes, outs, ins, asmstr, pattern>;
135 : IForm16<opcode, DstReg, SrcMem, Size4Bytes, outs, ins, asmstr, pattern>;
/external/llvm/lib/Target/ARM/
DARMExpandPseudoInsts.cpp388 unsigned DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandVLD() local
390 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); in ExpandVLD()
428 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandVLD()
516 unsigned DstReg = 0; in ExpandLaneOp() local
520 DstReg = MI.getOperand(OpIdx++).getReg(); in ExpandLaneOp()
521 GetDSubRegs(DstReg, RegSpc, TRI, D0, D1, D2, D3); in ExpandLaneOp()
570 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead)); in ExpandLaneOp()
617 unsigned DstReg = MI.getOperand(0).getReg(); in ExpandMOV32BitImm() local
626 LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg); in ExpandMOV32BitImm()
628 .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead)) in ExpandMOV32BitImm()
[all …]
/external/llvm/lib/Target/XCore/
DXCoreRegisterInfo.h32 unsigned DstReg, int64_t Value, DebugLoc dl) const;
40 unsigned DstReg, int Offset, DebugLoc dl) const;
/external/llvm/lib/Target/Mips/
DMipsSEISelDAGToDAG.cpp41 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
47 DstReg = MI.getOperand(0).getReg(); in replaceUsesWithZeroReg()
52 DstReg = MI.getOperand(0).getReg(); in replaceUsesWithZeroReg()
56 if (!DstReg) in replaceUsesWithZeroReg()
60 for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg), in replaceUsesWithZeroReg()
DMipsSEInstrInfo.cpp334 unsigned DstReg = I->getOperand(0).getReg(); in ExpandExtractElementF64() local
344 BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg); in ExpandExtractElementF64()
349 unsigned DstReg = I->getOperand(0).getReg(); in ExpandBuildPairF64() local
357 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven)) in ExpandBuildPairF64()
359 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd)) in ExpandBuildPairF64()
/external/llvm/lib/Target/PowerPC/
DPPCFrameLowering.cpp147 unsigned DstReg = MI->getOperand(0).getReg(); in HandleVRSaveUpdate() local
150 if (DstReg != SrcReg) in HandleVRSaveUpdate()
151 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
155 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORI), DstReg) in HandleVRSaveUpdate()
159 if (DstReg != SrcReg) in HandleVRSaveUpdate()
160 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
164 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
168 if (DstReg != SrcReg) in HandleVRSaveUpdate()
169 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
173 BuildMI(*MI->getParent(), MI, dl, TII.get(PPC::ORIS), DstReg) in HandleVRSaveUpdate()
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrInfo.cpp617 unsigned DstReg, unsigned SrcReg, unsigned ScratchReg, in emitRegUpdate() argument
619 if (NumBytes == 0 && DstReg == SrcReg) in emitRegUpdate()
656 BuildMI(MBB, MBBI, dl, TII.get(AddOp), DstReg) in emitRegUpdate()
682 BuildMI(MBB, MBBI, dl, TII.get(LowOp), DstReg) in emitRegUpdate()
688 SrcReg = DstReg; in emitRegUpdate()
692 BuildMI(MBB, MBBI, dl, TII.get(HighOp), DstReg) in emitRegUpdate()

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