| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 459 FCEIL, FTRUNC, FRINT, FNEARBYINT, FFLOOR, enumerator
|
| /external/llvm/lib/Target/R600/ |
| D | AMDGPUISelLowering.cpp | 47 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
147 return DAG.getNode(ISD::FRINT, DL, VT, Op.getOperand(1)); in LowerINTRINSIC_WO_CHAIN()
|
| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 665 setOperationAction(ISD::FRINT, MVT::f16, Expand); in TargetLoweringBase()
675 setOperationAction(ISD::FRINT, MVT::f32, Expand); in TargetLoweringBase()
685 setOperationAction(ISD::FRINT, MVT::f64, Expand); in TargetLoweringBase()
695 setOperationAction(ISD::FRINT, MVT::f128, Expand); in TargetLoweringBase()
|
| D | BasicTargetTransformInfo.cpp | 417 case Intrinsic::rint: ISD = ISD::FRINT; break; in getIntrinsicInstrCost()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 147 case ISD::FRINT: return "frint"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 242 case ISD::FRINT: in LegalizeOp()
|
| D | LegalizeFloatTypes.cpp | 90 case ISD::FRINT: R = SoftenFloatRes_FRINT(N); break; in SoftenFloatResult()
819 case ISD::FRINT: ExpandFloatRes_FRINT(N, Lo, Hi); break; in ExpandFloatResult()
|
| D | LegalizeVectorTypes.cpp | 85 case ISD::FRINT: in ScalarizeVectorResult()
541 case ISD::FRINT: in SplitVectorResult()
1437 case ISD::FRINT: in WidenVectorResult()
|
| D | SelectionDAGBuilder.cpp | 4898 case Intrinsic::rint: Opcode = ISD::FRINT; break; in visitIntrinsicCall()
5616 if (visitUnaryFloatCall(I, ISD::FRINT)) in visitCall()
|
| D | LegalizeDAG.cpp | 3216 case ISD::FRINT: in ExpandNode()
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64ISelLowering.cpp | 156 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AArch64TargetLowering()
157 setOperationAction(ISD::FRINT, MVT::f64, Legal); in AArch64TargetLowering()
220 setOperationAction(ISD::FRINT, MVT::f128, Expand); in AArch64TargetLowering()
|
| D | AArch64InstrInfo.td | 2031 // Contains: FMOV, FABS, FNEG, FSQRT, FCVT, FRINT[NPMZAXI].
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 380 def frint : SDNode<"ISD::FRINT" , SDTFPUnaryOp>;
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelLowering.cpp | 730 setOperationAction(ISD::FRINT, MVT::f80, Expand); in X86TargetLowering()
783 setOperationAction(ISD::FRINT, VT, Expand); in X86TargetLowering()
996 setOperationAction(ISD::FRINT, MVT::f32, Legal); in X86TargetLowering()
1001 setOperationAction(ISD::FRINT, MVT::f64, Legal); in X86TargetLowering()
1007 setOperationAction(ISD::FRINT, MVT::v4f32, Legal); in X86TargetLowering()
1012 setOperationAction(ISD::FRINT, MVT::v2f64, Legal); in X86TargetLowering()
1097 setOperationAction(ISD::FRINT, MVT::v8f32, Legal); in X86TargetLowering()
1110 setOperationAction(ISD::FRINT, MVT::v4f64, Legal); in X86TargetLowering()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 504 setOperationAction(ISD::FRINT, MVT::v2f64, Expand); in ARMTargetLowering()
521 setOperationAction(ISD::FRINT, MVT::v4f32, Expand); in ARMTargetLowering()
538 setOperationAction(ISD::FRINT, MVT::v2f32, Expand); in ARMTargetLowering()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 116 setOperationAction(ISD::FRINT, MVT::ppcf128, Expand); in PPCTargetLowering()
368 setOperationAction(ISD::FRINT, VT, Expand); in PPCTargetLowering()
|
| /external/llvm/lib/Target/ |
| D | README.txt | 528 We should add an FRINT node to the DAG to model targets that have legal
|