| /external/llvm/lib/CodeGen/ |
| D | BasicTargetTransformInfo.cpp | 72 int64_t BaseOffset, bool HasBaseReg,
130 int64_t BaseOffset, bool HasBaseReg, in isLegalAddressingMode() argument
135 AM.HasBaseReg = HasBaseReg; in isLegalAddressingMode()
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| D | TargetLoweringBase.cpp | 1294 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
1299 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
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| /external/llvm/lib/Target/X86/ |
| D | X86AsmPrinter.cpp | 277 bool HasBaseReg = BaseReg.getReg() != 0; in printLeaMemReference() local
278 if (HasBaseReg && Modifier && !strcmp(Modifier, "no-rip") && in printLeaMemReference()
280 HasBaseReg = false; in printLeaMemReference()
283 bool HasParenPart = IndexReg.getReg() || HasBaseReg; in printLeaMemReference()
303 if (HasBaseReg) in printLeaMemReference()
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| D | X86ISelLowering.cpp | 12583 if (AM.HasBaseReg && isGlobalRelativeToPICBase(GVFlags)) in isLegalAddressingMode()
12605 if (AM.HasBaseReg) in isLegalAddressingMode()
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| /external/llvm/lib/Analysis/ |
| D | TargetTransformInfo.cpp | 105 bool HasBaseReg, in isLegalAddressingMode() argument
107 return PrevTTI->isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, in isLegalAddressingMode()
452 bool HasBaseReg, int64_t Scale) const { in isLegalAddressingMode()
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| /external/llvm/lib/Transforms/Scalar/ |
| D | LoopStrengthReduce.cpp | 234 bool HasBaseReg; member
253 : BaseGV(0), BaseOffset(0), HasBaseReg(false), Scale(0), ScaledReg(0), in Formula()
340 HasBaseReg = true; in InitialMatch()
346 HasBaseReg = true; in InitialMatch()
408 if (HasBaseReg && BaseRegs.empty()) { in print()
411 } else if (!HasBaseReg && !BaseRegs.empty()) { in print()
1285 bool HasBaseReg, int64_t Scale) { in isLegalUse() argument
1288 return TTI.isLegalAddressingMode(AccessTy, BaseGV, BaseOffset, HasBaseReg, Scale); in isLegalUse()
1300 if (Scale != 0 && HasBaseReg && BaseOffset != 0) in isLegalUse()
1338 GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, in isLegalUse() argument
[all …]
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| D | CodeGenPrepare.cpp | 836 (HasBaseReg == O.HasBaseReg) && (Scale == O.Scale); in operator ==()
1140 if (AddrMode.HasBaseReg) { in MatchOperationAddr()
1145 AddrMode.HasBaseReg = true; in MatchOperationAddr()
1156 if (AddrMode.HasBaseReg) in MatchOperationAddr()
1158 AddrMode.HasBaseReg = true; in MatchOperationAddr()
1225 if (!AddrMode.HasBaseReg) { in MatchAddr()
1226 AddrMode.HasBaseReg = true; in MatchAddr()
1231 AddrMode.HasBaseReg = false; in MatchAddr()
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| /external/llvm/include/llvm/Analysis/ |
| D | TargetTransformInfo.h | 225 int64_t BaseOffset, bool HasBaseReg,
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| /external/llvm/include/llvm/Target/ |
| D | TargetLowering.h | 1139 bool HasBaseReg; member
1141 AddrMode() : BaseGV(0), BaseOffs(0), HasBaseReg(false), Scale(0) {} in AddrMode()
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| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 1342 if (AM.BaseOffs || AM.HasBaseReg || AM.Scale) in isLegalAddressingMode()
1351 if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed. in isLegalAddressingMode()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 1596 return Size >= 4 && !AM.HasBaseReg && AM.Scale == 0 && in isLegalAddressingMode()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 6744 if (AM.HasBaseReg && AM.BaseOffs) // "r+r+i" is not allowed. in isLegalAddressingMode()
6749 if (AM.HasBaseReg || AM.BaseOffs) // 2*r+r or 2*r+i is not allowed. in isLegalAddressingMode()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 3292 if (!AM.HasBaseReg) // allow "r+i". in isLegalAddressingMode()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 9670 if (((unsigned)AM.HasBaseReg + Scale) <= 2) in isLegalT2ScaledAddressingMode()
9728 if (((unsigned)AM.HasBaseReg + Scale) <= 2) in isLegalAddressingMode()
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