| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCInst.h | 27 const MCInstrDesc *MCID;
35 HexagonMCInst(const MCInstrDesc& mcid): in HexagonMCInst()
50 void setDesc(const MCInstrDesc& mcid) { MCID = &mcid; }; in setDesc()
51 const MCInstrDesc& getDesc(void) const { return *MCID; }; in getDesc()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 26 class MCInstrDesc; variable
225 const MCInstrDesc &MCID) { in BuildMI()
234 const MCInstrDesc &MCID, in BuildMI()
247 const MCInstrDesc &MCID, in BuildMI()
258 const MCInstrDesc &MCID, in BuildMI()
269 const MCInstrDesc &MCID, in BuildMI()
287 const MCInstrDesc &MCID) { in BuildMI()
297 const MCInstrDesc &MCID) { in BuildMI()
307 const MCInstrDesc &MCID) { in BuildMI()
323 const MCInstrDesc &MCID) { in BuildMI()
[all …]
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| D | DFAPacketizer.h | 35 class MCInstrDesc; variable
68 bool canReserveResources(const llvm::MCInstrDesc *MID);
72 void reserveResources(const llvm::MCInstrDesc *MID);
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| D | MachineInstr.h | 70 const MCInstrDesc *MCID; // Instruction descriptor.
112 MachineInstr(MachineFunction&, const MCInstrDesc &MCID,
257 const MCInstrDesc &getDesc() const { return *MCID; }
983 void setDesc(const MCInstrDesc &tid) { MCID = &tid; }
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| D | ScheduleDAG.h | 38 class MCInstrDesc; variable
582 const MCInstrDesc *getInstrDesc(const SUnit *SU) const {
614 const MCInstrDesc *getNodeDesc(const SDNode *Node) const;
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| /external/llvm/include/llvm/MC/ |
| D | MCInstrInfo.h | 27 const MCInstrDesc *Desc; // Raw array to allow static init'n
35 void InitMCInstrInfo(const MCInstrDesc *D, const unsigned *NI, const char *ND, in InitMCInstrInfo()
48 const MCInstrDesc &get(unsigned Opcode) const { in get()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.h | 26 class MCInstrDesc; variable
54 const MCInstrDesc &II,
69 const MCInstrDesc *II,
80 const MCInstrDesc *II,
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| D | InstrEmitter.cpp | 132 const MCInstrDesc &II = TII->get(User->getMachineOpcode()); in EmitCopyFromReg()
208 const MCInstrDesc &II, in CreateVirtualRegisters()
298 const MCInstrDesc *II, in AddRegisterOperand()
308 const MCInstrDesc &MCID = MIB->getDesc(); in AddRegisterOperand()
360 const MCInstrDesc *II, in AddOperand()
596 const MCInstrDesc &II = TII->get(TargetOpcode::REG_SEQUENCE); in EmitRegSequence()
646 const MCInstrDesc &II = TII->get(TargetOpcode::DBG_VALUE); in EmitDbgValue()
717 const MCInstrDesc &II = TII->get(Opc); in EmitMachineNode()
802 const MCInstrDesc &MCID = TII->get(F->getMachineOpcode()); in EmitMachineNode()
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| D | FastISel.cpp | 657 const MCInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE); in SelectCall()
1199 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_()
1209 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_r()
1229 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rr()
1251 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rrr()
1274 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_ri()
1295 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rii()
1318 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rf()
1340 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rri()
1364 const MCInstrDesc &II = TII.get(MachineInstOpcode); in FastEmitInst_rrii()
[all …]
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| /external/llvm/lib/Target/ARM/ |
| D | ARMHazardRecognizer.cpp | 22 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
43 const MCInstrDesc &MCID = MI->getDesc(); in getHazardType()
46 const MCInstrDesc &LastMCID = LastMI->getDesc(); in getHazardType()
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| D | ARMBaseInstrInfo.h | 248 const MCInstrDesc &DefMCID,
252 const MCInstrDesc &DefMCID,
256 const MCInstrDesc &UseMCID,
260 const MCInstrDesc &UseMCID,
264 const MCInstrDesc &DefMCID,
266 const MCInstrDesc &UseMCID,
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| D | ARMCodeEmitter.cpp | 101 const MCInstrDesc &MCID,
107 const MCInstrDesc &MCID) const;
279 const MCInstrDesc &MCID = MI.getDesc(); in getHiLo16ImmOpValue()
485 const MCInstrDesc &MCID = MI.getDesc(); in getMachineOpValue()
821 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelInstruction()
848 const MCInstrDesc &MCID = MI.getDesc(); in emitLEApcrelJTInstruction()
1015 const MCInstrDesc &MCID, in getMachineSoRegOpValue()
1085 const MCInstrDesc &MCID) const { in getAddrModeSBit()
1097 const MCInstrDesc &MCID = MI.getDesc(); in emitDataProcessingInstruction()
1200 const MCInstrDesc &MCID = MI.getDesc(); in emitLoadStoreInstruction()
[all …]
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| D | MLxExpansionPass.cpp | 186 const MCInstrDesc &MCID = MI->getDesc(); in hasRAWHazard()
286 const MCInstrDesc &MCID1 = TII->get(MulOpc); in ExpandFPMLxInstruction()
287 const MCInstrDesc &MCID2 = TII->get(AddSubOpc); in ExpandFPMLxInstruction()
343 const MCInstrDesc &MCID = MI->getDesc(); in ExpandFPMLxInstructions()
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| D | Thumb2SizeReduction.cpp | 203 static bool HasImplicitCPSRDef(const MCInstrDesc &MCID) { in HasImplicitCPSRDef()
523 const MCInstrDesc &MCID = MI->getDesc(); in ReduceSpecial()
659 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc2); in ReduceTo2Addr()
673 const MCInstrDesc &MCID = MI->getDesc(); in ReduceTo2Addr()
738 const MCInstrDesc &MCID = MI->getDesc(); in ReduceToNarrow()
757 const MCInstrDesc &NewMCID = TII->get(Entry.NarrowOpc1); in ReduceToNarrow()
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| D | Thumb1RegisterInfo.cpp | 241 const MCInstrDesc &MCID = TII.get(isSub ? ARM::tSUBi3 : ARM::tADDi3); in emitThumbRegPlusImmediate()
291 const MCInstrDesc &MCID = TII.get(ExtraOpc); in emitThumbRegPlusImmediate()
319 const MCInstrDesc &MCID = TII.get(ARM::tRSB); in emitThumbConstant()
354 const MCInstrDesc &Desc = MI.getDesc(); in rewriteFrameIndex()
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| D | ARMBaseInstrInfo.cpp | 152 const MCInstrDesc &MCID = MI->getDesc(); in convertToThreeAddress()
557 const MCInstrDesc &MCID = MI->getDesc(); in GetInstSizeInBytes()
1699 const MCInstrDesc &DefDesc = DefMI->getDesc(); in optimizeSelect()
1806 const MCInstrDesc &Desc = MI.getDesc(); in rewriteARMFrameIndex()
2282 const MCInstrDesc &DefMCID = DefMI->getDesc(); in FoldImmediate()
2292 const MCInstrDesc &UseMCID = UseMI->getDesc(); in FoldImmediate()
2388 const MCInstrDesc &Desc = MI->getDesc(); in getNumMicroOpsSwiftLdSt()
2644 const MCInstrDesc &Desc = MI->getDesc(); in getNumMicroOps()
2784 const MCInstrDesc &DefMCID, in getVLDMDefCycle()
2825 const MCInstrDesc &DefMCID, in getLDMDefCycle()
[all …]
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| D | ARMBaseRegisterInfo.cpp | 406 const MCInstrDesc &Desc = MI->getDesc(); in getFrameIndexInstrOffset()
553 const MCInstrDesc &MCID = TII.get(ADDriOpc); in materializeFrameBaseRegister()
595 const MCInstrDesc &Desc = MI->getDesc(); in isFrameOffsetLegal()
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| /external/llvm/lib/Target/R600/MCTargetDesc/ |
| D | SIMCCodeEmitter.cpp | 46 bool isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const;
76 bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc, in isSrcOperand()
133 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in EncodeInstruction()
191 const MCInstrDesc &Desc = MCII.get(MI.getOpcode()); in getMachineOpValue()
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| /external/llvm/lib/CodeGen/ |
| D | DFAPacketizer.cpp | 66 bool DFAPacketizer::canReserveResources(const llvm::MCInstrDesc *MID) { in canReserveResources()
78 void DFAPacketizer::reserveResources(const llvm::MCInstrDesc *MID) { in reserveResources()
92 const llvm::MCInstrDesc &MID = MI->getDesc(); in canReserveResources()
99 const llvm::MCInstrDesc &MID = MI->getDesc(); in reserveResources()
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| D | ScoreboardHazardRecognizer.cpp | 128 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in getHazardType()
184 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
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| D | TargetInstrInfo.cpp | 39 TargetInstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum, in getRegClass()
120 const MCInstrDesc &MCID = MI->getDesc(); in commuteInstruction()
185 const MCInstrDesc &MCID = MI->getDesc(); in findCommutedOpIndices()
220 const MCInstrDesc &MCID = MI->getDesc(); in PredicateInstruction()
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCHazardRecognizers.cpp | 27 const MCInstrDesc *MCID = DAG->getInstrDesc(SU); in EmitInstruction()
94 const MCInstrDesc &MCID = TII.get(Opcode); in GetInstrType()
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| /external/llvm/lib/Target/X86/ |
| D | X86CodeEmitter.cpp | 72 const MCInstrDesc *Desc) const;
76 const MCInstrDesc *Desc) const;
82 void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc);
151 const MCInstrDesc &Desc = I->getDesc(); in runOnMachineFunction()
169 const MCInstrDesc &Desc = MI.getDesc(); in determineREX()
610 static const MCInstrDesc *UpdateOp(MachineInstr &MI, const X86InstrInfo *II, in UpdateOp()
612 const MCInstrDesc *Desc = &II->get(Opcode); in UpdateOp()
665 const MCInstrDesc *Desc) const { in emitOpcodePrefix()
816 const MCInstrDesc *Desc) const { in emitVEXOpcodePrefix()
1105 const MCInstrDesc *Desc) { in emitInstruction()
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| /external/llvm/lib/Target/Mips/ |
| D | Mips16InstrInfo.h | 97 const MCInstrDesc& AddiuSpImm(int64_t Imm) const;
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| /external/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCCodeEmitter.cpp | 127 const MCInst &MI, const MCInstrDesc &Desc,
135 const MCInst &MI, const MCInstrDesc &Desc,
445 const MCInstrDesc &Desc, in EmitVEXOpcodePrefix()
734 const MCInstrDesc &Desc) { in DetermineREXPrefix()
861 const MCInstrDesc &Desc, in EmitOpcodePrefix()
975 const MCInstrDesc &Desc = MCII.get(Opcode); in EncodeInstruction()
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