/external/llvm/lib/Target/Mips/ |
D | MipsSEInstrInfo.cpp | 44 unsigned Opc = MI->getOpcode(); in isLoadFromStackSlot() local 46 if ((Opc == Mips::LW) || (Opc == Mips::LW_P8) || (Opc == Mips::LD) || in isLoadFromStackSlot() 47 (Opc == Mips::LD_P8) || (Opc == Mips::LWC1) || (Opc == Mips::LWC1_P8) || in isLoadFromStackSlot() 48 (Opc == Mips::LDC1) || (Opc == Mips::LDC164) || in isLoadFromStackSlot() 49 (Opc == Mips::LDC164_P8)) { in isLoadFromStackSlot() 69 unsigned Opc = MI->getOpcode(); in isStoreToStackSlot() local 71 if ((Opc == Mips::SW) || (Opc == Mips::SW_P8) || (Opc == Mips::SD) || in isStoreToStackSlot() 72 (Opc == Mips::SD_P8) || (Opc == Mips::SWC1) || (Opc == Mips::SWC1_P8) || in isStoreToStackSlot() 73 (Opc == Mips::SDC1) || (Opc == Mips::SDC164) || in isStoreToStackSlot() 74 (Opc == Mips::SDC164_P8)) { in isStoreToStackSlot() [all …]
|
D | Mips16InstrInfo.cpp | 72 unsigned Opc = 0; in copyPhysReg() local 76 Opc = Mips::MoveR3216; in copyPhysReg() 79 Opc = Mips::Move32R16; in copyPhysReg() 82 Opc = Mips::Mfhi16, SrcReg = 0; in copyPhysReg() 86 Opc = Mips::Mflo16, SrcReg = 0; in copyPhysReg() 89 assert(Opc && "Cannot copy registers"); in copyPhysReg() 91 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); in copyPhysReg() 108 unsigned Opc = 0; in storeRegToStackSlot() local 110 Opc = Mips::SwRxSpImmX16; in storeRegToStackSlot() 111 assert(Opc && "Register class not handled!"); in storeRegToStackSlot() [all …]
|
D | Mips16ISelDAGToDAG.cpp | 40 Mips16DAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty, in selectMULT() argument 43 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0), in selectMULT() 248 unsigned Opc = InFlag.getOpcode(); (void)Opc; in selectNode() local 249 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectNode() 250 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectNode()
|
D | MipsSEISelDAGToDAG.cpp | 182 MipsSEDAGToDAGISel::selectMULT(SDNode *N, unsigned Opc, DebugLoc DL, EVT Ty, in selectMULT() argument 185 SDNode *Mul = CurDAG->getMachineNode(Opc, DL, MVT::Glue, N->getOperand(0), in selectMULT() 204 unsigned Opc = InFlag.getOpcode(); (void)Opc; in selectAddESubE() local 206 assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) || in selectAddESubE() 207 (Opc == ISD::SUBC || Opc == ISD::SUBE)) && in selectAddESubE() 410 if (Inst->Opc == Mips::LUi64) in selectNode() 411 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd); in selectNode() 414 CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, in selectNode() 422 RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, in selectNode()
|
D | MipsSEInstrInfo.h | 66 virtual unsigned GetOppositeBranchOpc(unsigned Opc) const; 80 virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const; 83 unsigned Opc) const;
|
D | MipsAnalyzeImmediate.cpp | 15 MipsAnalyzeImmediate::Inst::Inst(unsigned O, unsigned I) : Opc(O), ImmOpnd(I) {} in Inst() 88 if ((Seq.size() < 2) || (Seq[0].Opc != ADDiu) || in ReplaceADDiuSLLWithLUi() 89 (Seq[1].Opc != SLL) || (Seq[1].ImmOpnd < 16)) in ReplaceADDiuSLLWithLUi() 100 Seq[0].Opc = LUi; in ReplaceADDiuSLLWithLUi()
|
D | MipsInstrInfo.h | 84 virtual unsigned GetOppositeBranchOpc(unsigned Opc) const = 0; 96 virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const = 0; 98 void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
|
D | Mips16InstrInfo.h | 65 virtual unsigned GetOppositeBranchOpc(unsigned Opc) const; 103 virtual unsigned GetAnalyzableBrOpc(unsigned Opc) const; 106 unsigned Opc) const;
|
/external/llvm/lib/Target/ARM/ |
D | ARMBaseInstrInfo.h | 43 virtual unsigned getUnindexedOpcode(unsigned Opc) const =0; 341 bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode() argument 342 return Opc == ARM::B || Opc == ARM::tB || Opc == ARM::t2B; in isUncondBranchOpcode() 346 bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode() argument 347 return Opc == ARM::Bcc || Opc == ARM::tBcc || Opc == ARM::t2Bcc; in isCondBranchOpcode() 351 bool isJumpTableBranchOpcode(int Opc) { in isJumpTableBranchOpcode() argument 352 return Opc == ARM::BR_JTr || Opc == ARM::BR_JTm || Opc == ARM::BR_JTadd || in isJumpTableBranchOpcode() 353 Opc == ARM::tBR_JTr || Opc == ARM::t2BR_JT; in isJumpTableBranchOpcode() 357 bool isIndirectBranchOpcode(int Opc) { in isIndirectBranchOpcode() argument 358 return Opc == ARM::BX || Opc == ARM::MOVPCRX || Opc == ARM::tBRIND; in isIndirectBranchOpcode() [all …]
|
D | ARMISelDAGToDAG.cpp | 113 bool SelectLdStSOReg(SDValue N, SDValue &Base, SDValue &Offset, SDValue &Opc); 116 SDValue &Offset, SDValue &Opc); 118 SDValue &Opc) { in SelectAddrMode2Base() argument 119 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_BASE; in SelectAddrMode2Base() 123 SDValue &Opc) { in SelectAddrMode2ShOp() argument 124 return SelectAddrMode2Worker(N, Base, Offset, Opc) == AM2_SHOP; in SelectAddrMode2ShOp() 128 SDValue &Opc) { in SelectAddrMode2() argument 129 SelectAddrMode2Worker(N, Base, Offset, Opc); in SelectAddrMode2() 136 SDValue &Offset, SDValue &Opc); 138 SDValue &Offset, SDValue &Opc); [all …]
|
D | ARMFastISel.cpp | 522 unsigned Opc; in ARMMaterializeFP() local 525 Opc = ARM::FCONSTD; in ARMMaterializeFP() 528 Opc = ARM::FCONSTS; in ARMMaterializeFP() 531 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), in ARMMaterializeFP() 548 unsigned Opc = is64bit ? ARM::VLDRD : ARM::VLDRS; in ARMMaterializeFP() local 551 AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), in ARMMaterializeFP() 567 unsigned Opc = isThumb2 ? ARM::t2MOVi16 : ARM::MOVi16; in ARMMaterializeInt() local 572 TII.get(Opc), ImmReg) in ARMMaterializeInt() 583 unsigned Opc = isThumb2 ? ARM::t2MVNi : ARM::MVNi; in ARMMaterializeInt() local 586 TII.get(Opc), ImmReg) in ARMMaterializeInt() [all …]
|
D | ARMInstrInfo.cpp | 52 unsigned ARMInstrInfo::getUnindexedOpcode(unsigned Opc) const { in getUnindexedOpcode() 53 switch (Opc) { in getUnindexedOpcode() 122 unsigned Opc = TM->getSubtarget<ARMSubtarget>().isThumb2() ? in runOnMachineFunction() local 126 TII.get(Opc), GlobalBaseReg) in runOnMachineFunction() 128 if (Opc == ARM::LDRcp) in runOnMachineFunction()
|
D | Thumb2SizeReduction.cpp | 307 unsigned Opc = MI->getOpcode(); in VerifyLowRegs() local 308 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA || in VerifyLowRegs() 309 Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD || in VerifyLowRegs() 310 Opc == ARM::t2LDMDB_UPD); in VerifyLowRegs() 311 bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD); in VerifyLowRegs() 327 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12)) in VerifyLowRegs() 348 unsigned Opc = Entry.NarrowOpc1; in ReduceLoadStore() local 358 Opc = Entry.NarrowOpc2; in ReduceLoadStore() 416 Opc = Entry.NarrowOpc2; // tPOP_RET in ReduceLoadStore() 431 Opc = Entry.NarrowOpc2; // tPOP or tPUSH in ReduceLoadStore() [all …]
|
D | Thumb1RegisterInfo.cpp | 129 int Opc = (isSub) ? ARM::tSUBrr : (isHigh ? ARM::tADDhirr : ARM::tADDrr); in emitThumbRegPlusImmInReg() local 131 BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg); in emitThumbRegPlusImmInReg() 132 if (Opc != ARM::tADDhirr) in emitThumbRegPlusImmInReg() 143 static unsigned calcNumMI(int Opc, int ExtraOpc, unsigned Bytes, in calcNumMI() argument 148 if (Opc == ARM::tADDrSPi) { in calcNumMI() 182 int Opc = 0; in emitThumbRegPlusImmediate() local 190 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitThumbRegPlusImmediate() 203 Opc = ARM::tADDrSPi; in emitThumbRegPlusImmediate() 212 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitThumbRegPlusImmediate() 217 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8; in emitThumbRegPlusImmediate() [all …]
|
D | Thumb2InstrInfo.cpp | 43 unsigned Thumb2InstrInfo::getUnindexedOpcode(unsigned Opc) const { in getUnindexedOpcode() 226 unsigned Opc = 0; in emitT2RegPlusImmediate() local 240 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitT2RegPlusImmediate() 241 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitT2RegPlusImmediate() 248 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; in emitT2RegPlusImmediate() 261 Opc = isSub ? ARM::t2SUBri : ARM::t2ADDri; in emitT2RegPlusImmediate() 265 Opc = isSub ? ARM::t2SUBri12 : ARM::t2ADDri12; in emitT2RegPlusImmediate() 280 AddDefaultPred(BuildMI(MBB, MBBI, dl, TII.get(Opc), DestReg) in emitT2RegPlusImmediate() 568 unsigned Opc = MI->getOpcode(); in getITInstrPredicate() local 569 if (Opc == ARM::tBcc || Opc == ARM::t2Bcc) in getITInstrPredicate()
|
/external/llvm/lib/Target/Hexagon/ |
D | HexagonCFGOptimizer.cpp | 54 static bool IsConditionalBranch(int Opc) { in IsConditionalBranch() argument 55 return (Opc == Hexagon::JMP_c) || (Opc == Hexagon::JMP_cNot) in IsConditionalBranch() 56 || (Opc == Hexagon::JMP_cdnPt) || (Opc == Hexagon::JMP_cdnNotPt); in IsConditionalBranch() 60 static bool IsUnconditionalJump(int Opc) { in IsUnconditionalJump() argument 61 return (Opc == Hexagon::JMP); in IsUnconditionalJump() 107 int Opc = MI->getOpcode(); in runOnMachineFunction() local 108 if (IsConditionalBranch(Opc)) { in runOnMachineFunction()
|
/external/llvm/lib/Target/X86/ |
D | X86FrameLowering.cpp | 107 unsigned Opc = MBBI->getOpcode(); in findDeadCallerSavedReg() local 108 switch (Opc) { in findDeadCallerSavedReg() 152 unsigned Opc; in emitSPUpdate() local 154 Opc = getLEArOpcode(IsLP64); in emitSPUpdate() 156 Opc = isSub in emitSPUpdate() 171 Opc = isSub in emitSPUpdate() 174 MachineInstr *MI = BuildMI(MBB, MBBI, DL, TII.get(Opc)) in emitSPUpdate() 186 MI = addRegOffset(BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr), in emitSPUpdate() 189 MI = BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) in emitSPUpdate() 209 unsigned Opc = PI->getOpcode(); in mergeSPUpdatesUp() local [all …]
|
D | X86ISelDAGToDAG.cpp | 189 SDNode *SelectGather(SDNode *N, unsigned Opc); 190 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc); 1491 SDNode *X86DAGToDAGISel::SelectAtomic64(SDNode *Node, unsigned Opc) { in SelectAtomic64() argument 1503 SDNode *ResNode = CurDAG->getMachineNode(Opc, Node->getDebugLoc(), in SelectAtomic64() 1726 unsigned Opc = 0; in SelectAtomicLoadArith() local 1731 Opc = AtomicOpcTbl[Op][ConstantI8]; in SelectAtomicLoadArith() 1733 Opc = AtomicOpcTbl[Op][I8]; in SelectAtomicLoadArith() 1738 Opc = AtomicOpcTbl[Op][SextConstantI16]; in SelectAtomicLoadArith() 1740 Opc = AtomicOpcTbl[Op][ConstantI16]; in SelectAtomicLoadArith() 1742 Opc = AtomicOpcTbl[Op][I16]; in SelectAtomicLoadArith() [all …]
|
D | X86FastISel.cpp | 90 bool X86FastEmitExtend(ISD::NodeType Opc, EVT DstVT, unsigned Src, EVT SrcVT, 183 unsigned Opc = 0; in X86FastEmitLoad() local 189 Opc = X86::MOV8rm; in X86FastEmitLoad() 193 Opc = X86::MOV16rm; in X86FastEmitLoad() 197 Opc = X86::MOV32rm; in X86FastEmitLoad() 202 Opc = X86::MOV64rm; in X86FastEmitLoad() 207 Opc = Subtarget->hasAVX() ? X86::VMOVSSrm : X86::MOVSSrm; in X86FastEmitLoad() 210 Opc = X86::LD_Fp32m; in X86FastEmitLoad() 216 Opc = Subtarget->hasAVX() ? X86::VMOVSDrm : X86::MOVSDrm; in X86FastEmitLoad() 219 Opc = X86::LD_Fp64m; in X86FastEmitLoad() [all …]
|
D | X86InstrInfo.cpp | 1730 unsigned Opc = Orig->getOpcode(); in reMaterialize() local 1731 switch (Opc) { in reMaterialize() 1738 switch (Opc) { in reMaterialize() 1740 case X86::MOV8r0: Opc = X86::MOV8ri; break; in reMaterialize() 1741 case X86::MOV16r0: Opc = X86::MOV16ri; break; in reMaterialize() 1742 case X86::MOV32r0: Opc = X86::MOV32ri; break; in reMaterialize() 1743 case X86::MOV64r0: Opc = X86::MOV64ri64i32; break; in reMaterialize() 1755 BuildMI(MBB, I, DL, get(Opc)).addOperand(Orig->getOperand(0)).addImm(0); in reMaterialize() 1790 unsigned Opc = TM.getSubtarget<X86Subtarget>().is64Bit() in convertToThreeAddressWithLEA() local 1810 get(Opc), leaOutReg); in convertToThreeAddressWithLEA() [all …]
|
/external/llvm/utils/TableGen/ |
D | FixedLenDecoderEmitter.cpp | 421 void SingletonExists(unsigned Opc) const; 439 unsigned Opc) const; 441 bool doesOpcodeNeedPredicate(unsigned Opc) const; 444 unsigned Opc) const; 447 unsigned Opc) const; 451 unsigned Opc) const; 460 void emitDecoder(raw_ostream &OS, unsigned Indentation, unsigned Opc) const; 461 unsigned getDecoderIndex(DecoderSet &Decoders, unsigned Opc) const; 819 unsigned Opc = decodeULEB128(Buffer); in emitTable() local 831 << NumberedInstructions->at(Opc)->TheDef->getName() << "\n"; in emitTable() [all …]
|
/external/llvm/lib/Target/AArch64/Disassembler/ |
D | AArch64Disassembler.cpp | 465 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc; in DecodeBitfieldInstruction() local 466 Opc = (OpcTypes)fieldFromInstruction(Insn, 29, 2); in DecodeBitfieldInstruction() 477 if (Opc == BFM) DecodeGPR64RegisterClass(Inst, Rd, Address, Decoder); in DecodeBitfieldInstruction() 482 if (Opc == BFM) DecodeGPR32RegisterClass(Inst, Rd, Address, Decoder); in DecodeBitfieldInstruction() 487 assert(!(ImmS == 31 && !SF && Opc != BFM) in DecodeBitfieldInstruction() 489 assert(!(ImmS == 63 && SF && Opc != BFM) in DecodeBitfieldInstruction() 493 if (Opc == SBFM && ImmR == 0) { in DecodeBitfieldInstruction() 496 } else if (Opc == UBFM && ImmR == 0) { in DecodeBitfieldInstruction() 500 if (Opc == UBFM) { in DecodeBitfieldInstruction() 517 switch (Opc) { in DecodeBitfieldInstruction() [all …]
|
/external/llvm/include/llvm/IR/ |
D | InstrTypes.h | 194 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, 196 BinaryOperator *BO = Create(Opc, V1, V2, Name); 200 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, 202 BinaryOperator *BO = Create(Opc, V1, V2, Name, BB); 206 static BinaryOperator *CreateNSW(BinaryOps Opc, Value *V1, Value *V2, 208 BinaryOperator *BO = Create(Opc, V1, V2, Name, I); 213 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2, 215 BinaryOperator *BO = Create(Opc, V1, V2, Name); 219 static BinaryOperator *CreateNUW(BinaryOps Opc, Value *V1, Value *V2, 221 BinaryOperator *BO = Create(Opc, V1, V2, Name, BB); [all …]
|
/external/llvm/lib/Target/MBlaze/ |
D | MBlazeInstrInfo.h | 144 inline static bool isUncondBranchOpcode(int Opc) { in isUncondBranchOpcode() argument 145 switch (Opc) { in isUncondBranchOpcode() 155 inline static bool isCondBranchOpcode(int Opc) { in isCondBranchOpcode() argument 156 switch (Opc) { in isCondBranchOpcode()
|
/external/llvm/lib/Target/ARM/MCTargetDesc/ |
D | ARMAddressingModes.h | 407 static inline unsigned getAM2Opc(AddrOpc Opc, unsigned Imm12, ShiftOpc SO, 410 bool isSub = Opc == sub; 442 static inline unsigned getAM3Opc(AddrOpc Opc, unsigned char Offset, 444 bool isSub = Opc == sub; 492 static inline unsigned getAM5Opc(AddrOpc Opc, unsigned char Offset) { in getAM5Opc() argument 493 bool isSub = Opc == sub; in getAM5Opc()
|