| /external/skia/include/core/ |
| D | SkChecksum.h | 20 ROTR = 17, enumerator
21 ROTL = sizeof(uintptr_t) * 8 - ROTR,
26 return ((total >> ROTR) | (total << ROTL)) ^ value; in Mash()
|
| /external/openssl/crypto/sha/ |
| D | sha512.c | 309 # define ROTR(a,n) ({ SHA_LONG64 ret; \ macro
339 # define ROTR(a,n) ({ SHA_LONG64 ret; \ macro
347 # define ROTR(a,n) _rotr64((a),n) macro
382 #ifndef ROTR
383 #define ROTR(x,s) (((x)>>s) | (x)<<(64-s)) macro
386 #define Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
387 #define Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
388 #define sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
389 #define sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6))
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMSelectionDAGInfo.h | 29 case ISD::ROTR: return ARM_AM::ror; in getShiftOpcForNode()
|
| /external/openssl/crypto/sha/asm/ |
| D | sha512-armv4.S | 131 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
186 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
225 @ sigma0(x) (ROTR((x),1) ^ ROTR((x),8) ^ ((x)>>7))
242 @ sigma1(x) (ROTR((x),19) ^ ROTR((x),61) ^ ((x)>>6))
268 @ Sigma1(x) (ROTR((x),14) ^ ROTR((x),18) ^ ROTR((x),41))
323 @ Sigma0(x) (ROTR((x),28) ^ ROTR((x),34) ^ ROTR((x),39))
|
| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 318 SHL, SRA, SRL, ROTL, ROTR, enumerator
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 119 setOperationAction(ISD::ROTR , MVT::i64, Legal); in NVPTXTargetLowering()
123 setOperationAction(ISD::ROTR , MVT::i64, Expand); in NVPTXTargetLowering()
127 setOperationAction(ISD::ROTR , MVT::i32, Legal); in NVPTXTargetLowering()
131 setOperationAction(ISD::ROTR , MVT::i32, Expand); in NVPTXTargetLowering()
135 setOperationAction(ISD::ROTR , MVT::i16, Expand); in NVPTXTargetLowering()
137 setOperationAction(ISD::ROTR , MVT::i8, Expand); in NVPTXTargetLowering()
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | logical_shifted_reg.ll | 175 ; operations. DAGCombiner should ensure we the ROTR during
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGDumper.cpp | 176 case ISD::ROTR: return "rotr"; in getOperationName()
|
| D | LegalizeVectorOps.cpp | 212 case ISD::ROTR: in LegalizeOp()
|
| D | DAGCombiner.cpp | 3035 if (TLI.isOperationLegalOrCustom(ISD::ROTR, VT)) in MatchBSwapHWord()
3036 return DAG.getNode(ISD::ROTR, N->getDebugLoc(), VT, BSwap, ShAmt); in MatchBSwapHWord()
3227 bool HasROTR = TLI.isOperationLegalOrCustom(ISD::ROTR, VT); in MatchRotate()
3268 SDValue Rot = DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, in MatchRotate()
3302 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, LHSShiftArg, in MatchRotate()
3315 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, LHSShiftArg, in MatchRotate()
3341 return DAG.getNode(HasROTL ? ISD::ROTL : ISD::ROTR, DL, VT, in MatchRotate()
3355 return DAG.getNode(HasROTR ? ISD::ROTR : ISD::ROTL, DL, VT, in MatchRotate()
|
| D | SelectionDAG.cpp | 2216 case ISD::ROTR: in ComputeNumSignBits()
2221 if (Op.getOpcode() == ISD::ROTR) in ComputeNumSignBits()
2775 case ISD::ROTR: in FoldConstantArithmetic()
2910 case ISD::ROTR: in getNode()
6142 case ISD::ROTR: in UnrollVectorOp()
|
| D | LegalizeIntegerTypes.cpp | 800 case ISD::ROTR: Res = PromoteIntOp_Shift(N); break; in PromoteIntegerOperand()
2486 case ISD::ROTR: Res = ExpandIntOp_Shift(N); break; in ExpandIntegerOperand()
|
| D | LegalizeDAG.cpp | 1277 case ISD::ROTR: in LegalizeOp()
|
| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 102 setOperationAction(ISD::ROTR, MVT::i8, Expand); in MSP430TargetLowering()
104 setOperationAction(ISD::ROTR, MVT::i16, Expand); in MSP430TargetLowering()
|
| /external/llvm/lib/Target/R600/ |
| D | AMDILISelLowering.cpp | 142 setOperationAction(ISD::ROTR, VT, Expand); in InitAMDILLowering()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsInstrInfo.td | 840 def ROTR : shift_rotate_imm<"rotr", shamt, CPURegsOpnd, rotr, immZExt5>,
1221 def : MipsPat<(bswap CPURegs:$rt), (ROTR (WSBH CPURegs:$rt), 16)>;
|
| D | MipsISelLowering.cpp | 304 setOperationAction(ISD::ROTR, MVT::i32, Expand); in MipsTargetLowering()
307 setOperationAction(ISD::ROTR, MVT::i64, Expand); in MipsTargetLowering()
|
| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 167 setOperationAction(ISD::ROTR, MVT::i32, Expand); in MBlazeTargetLowering()
|
| /external/llvm/lib/Target/X86/ |
| D | X86InstrShiftRotate.td | 847 // Convert a ROTL shamt to a ROTR shamt on 32-bit integer.
852 // Convert a ROTL shamt to a ROTR shamt on 64-bit integer.
|
| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 773 setOperationAction(ISD::ROTR , MVT::i32, Expand); in SparcTargetLowering()
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1423 setOperationAction(ISD::ROTR , MVT::i32, Expand); in HexagonTargetLowering()
|
| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 334 def rotr : SDNode<"ISD::ROTR" , SDTIntShiftOp>;
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 111 setOperationAction(ISD::ROTR , MVT::i32, Expand); in XCoreTargetLowering()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 173 setOperationAction(ISD::ROTR, MVT::i32 , Expand); in PPCTargetLowering()
174 setOperationAction(ISD::ROTR, MVT::i64 , Expand); in PPCTargetLowering()
|
| /external/valgrind/main/none/tests/mips32/ |
| D | MIPS32int.stdout.exp-BE | 664 ROTR
|