| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb.td | 316 let Inst{6-3} = 0b1111; // Rm = pc
367 // ADD <Rm>, sp
379 // ADD sp, <Rm>
380 def tADDspr : T1pIt<(outs GPRsp:$Rdn), (ins GPRsp:$Rn, GPR:$Rm), IIC_iALUr,
381 "add", "\t$Rdn, $Rm", []>,
384 bits<4> Rm;
386 let Inst{6-3} = Rm;
397 def tBX : TI<(outs), (ins GPR:$Rm, pred:$p), IIC_Br, "bx${p}\t$Rm", []>,
400 bits<4> Rm;
401 let Inst{6-3} = Rm;
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| D | ARMInstrThumb2.td | 265 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
271 let MIOperandInfo = (ops GPR:$Rn, rGPR:$Rm);
361 bits<4> Rm;
364 let Inst{3-0} = Rm;
371 bits<4> Rm;
374 let Inst{3-0} = Rm;
381 bits<4> Rm;
384 let Inst{3-0} = Rm;
420 bits<4> Rm;
424 let Inst{3-0} = Rm;
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| D | ARMInstrInfo.td | 1023 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1024 iir, opc, "\t$Rd, $Rn, $Rm",
1025 [(set GPR:$Rd, (opnode GPR:$Rn, GPR:$Rm))]> {
1028 bits<4> Rm;
1034 let Inst{3-0} = Rm;
1092 def rr : AsI1<opcod, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm), DPFrm,
1093 iir, opc, "\t$Rd, $Rn, $Rm",
1097 bits<4> Rm;
1100 let Inst{3-0} = Rm;
1150 def rr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm, pred:$p),
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| D | ARMInstrNEON.td | 627 let Rm = 0b1111;
635 let Rm = 0b1111;
656 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
662 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1u,
663 "vld1", Dt, "$Vd, $Rn, $Rm",
675 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
681 (ins addrmode6:$Rn, rGPR:$Rm), IIC_VLD1x2u,
682 "vld1", Dt, "$Vd, $Rn, $Rm",
704 let Rm = 0b1111;
713 let Rm = 0b1101; // NLdSt will assign to the right encoding bits.
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| D | ARMInstrFormats.td | 598 // {11-0} imm12/Rm
616 // {11-0} imm12/Rm
635 // {13} 1 == Rm, 0 == imm12
637 // {11-0} imm12/Rm
655 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
662 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
687 // {13} 1 == imm8, 0 == Rm
691 // {3-0} imm3_0/Rm
713 let Inst{22} = addr{13}; // 1 == imm8, 0 == Rm
720 let Inst{3-0} = addr{3-0}; // imm3_0/Rm
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| D | ARMBaseInstrInfo.cpp | 2432 unsigned Rm = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
2433 return (Rt == Rm) ? 4 : 3; in getNumMicroOpsSwiftLdSt()
2439 unsigned Rm = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
2440 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
2469 unsigned Rm = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
2470 if (!Rm) in getNumMicroOpsSwiftLdSt()
2472 if (Rt == Rm) in getNumMicroOpsSwiftLdSt()
2482 unsigned Rm = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
2483 return (Rt == Rm) ? 3 : 2; in getNumMicroOpsSwiftLdSt()
2501 unsigned Rm = MI->getOperand(3).getReg(); in getNumMicroOpsSwiftLdSt() local
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 270 let uxtb = (and (anyext GPR32:$Rm), 255);
271 let uxth = (and (anyext GPR32:$Rm), 65535);
272 let uxtw = (zext GPR32:$Rm);
273 let uxtx = (i64 GPR64:$Rm);
275 let sxtb = (sext_inreg (anyext GPR32:$Rm), i8);
276 let sxth = (sext_inreg (anyext GPR32:$Rm), i16);
277 let sxtw = (sext GPR32:$Rm);
278 let sxtx = (i64 GPR64:$Rm);
283 let uxtb = (and GPR32:$Rm, 255);
284 let uxth = (and GPR32:$Rm, 65535);
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| D | AArch64InstrFormats.td | 118 bits<5> Rm;
120 let Inst{20-16} = Rm;
141 // Rm inherited in 20-16
176 // Rm inherited in 20-16
191 // Rm inherited in 20-16
274 bits<5> Rm;
283 let Inst{20-16} = Rm;
303 // Inherit Rm in 20-16
347 // Inherits Rm in 20-16
380 // Inherits Rm in bits 20-16
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| /external/llvm/lib/Target/ARM/Disassembler/ |
| D | ARMDisassembler.cpp | 1118 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegImmOperand() local
1123 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegImmOperand()
1155 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegRegOperand() local
1160 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegRegOperand()
1435 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode2IdxInstruction() local
1497 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder))) in DecodeAddrMode2IdxInstruction()
1539 unsigned Rm = fieldFromInstruction(Val, 0, 4); in DecodeSORegMemOperand() local
1565 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder))) in DecodeSORegMemOperand()
1584 unsigned Rm = fieldFromInstruction(Insn, 0, 4); in DecodeAddrMode3Instruction() local
1617 if (type && Rm == 15) in DecodeAddrMode3Instruction()
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| /external/qemu/ |
| D | trace.c | 894 int Rm = (insn & 15); in get_insn_ticks_arm() local
905 result += 2 + _interlock_use(Rm) + _interlock_use(Rs); in get_insn_ticks_arm()
909 int Rm = (insn & 15); in get_insn_ticks_arm() local
920 result += 3 + _interlock_use(Rm) + _interlock_use(Rs); in get_insn_ticks_arm()
924 int Rm = (insn & 15); in get_insn_ticks_arm() local
927 result = 2 + _interlock_use(Rm); in get_insn_ticks_arm()
932 int Rm = (insn & 15); in get_insn_ticks_arm() local
936 result += _interlock_use(Rn) + _interlock_use(Rm); in get_insn_ticks_arm()
955 int Rm = (insn & 15); in get_insn_ticks_arm() local
959 result += _interlock_use(Rn) + _interlock_use(Rm); in get_insn_ticks_arm()
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| D | i386-dis.c | 349 #define Rm { OP_R, m_mode } macro
1058 { "movZ", { Rm, Cm } },
1059 { "movZ", { Rm, Dm } },
1060 { "movZ", { Cm, Rm } },
1061 { "movZ", { Dm, Rm } },
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| D | arm-dis.c | 3465 unsigned int Rm = (i8 & 0x0f); in print_insn_thumb32() local
3467 func (stream, ", %s", arm_regnames[Rm]); in print_insn_thumb32()
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| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | a64-ignored-fields.txt | 3 # The "Rm" bits are ignored, but the canonical representation has them filled
|
| /external/qemu/distrib/sdl-1.2.15/src/video/ |
| D | SDL_pixels.c | 143 int Rm=0,Gm=0,Bm=0; in SDL_AllocFormat() local
152 Rm|=1<<i; in SDL_AllocFormat()
155 fprintf(stderr,"Rw=%d Rm=0x%02X\n",Rw,Rm); in SDL_AllocFormat()
189 r=(r<<format->Rloss)|((r*Rm)>>Rw); in SDL_AllocFormat()
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMMCCodeEmitter.cpp | 728 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue() local
729 return (Rm << 3) | Rn; in getThumbAddrModeRegRegOpValue()
944 unsigned Rm = CTX.getRegisterInfo().getEncodingValue(MO1.getReg()); in getLdStSORegOpValue() local
961 uint32_t Binary = Rm; in getLdStSORegOpValue()
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| /external/llvm/test/MC/ARM/ |
| D | thumb2-narrow-dp.ll | 5 // OP{S}{<c>}{<q>} {<Rd>,} <Rn>, <Rm>
8 // - Rd, Rn and Rm are < r8
11 // - Rd == Rn || Rd == Rm
12 // - Rd, Rn and Rm are < r8
|
| /external/valgrind/main/none/tests/arm/ |
| D | vfp.stdout.exp | 924 vstr d30, [r12] :: Dd 0xc2c2c2c2 0xc2c2c2c2 *(int*) (Rm + shift) 0xc2c2c2c2
929 vstr d18, [r3] :: Dd 0x33333333 0x33333333 *(int*) (Rm + shift) 0x33333333
931 vstr d17, [r10] :: Dd 0x77777777 0x77777777 *(int*) (Rm + shift) 0x77777777
936 vstr d8, [r4] :: Dd 0x1f1f1f1f 0x1f1f1f1f *(int*) (Rm + shift) 0x1f1f1f1f
942 vstr s29, [r8] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000
943 vstr s8, [r12] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000
948 vstr s11, [r2] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000
949 vstr s30, [r0] :: Sd 0xbe280000, *(int*) (Rm + shift) 0xbe280000
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| D | v6intThumb.stdout.exp | 567 ADDS-16 Rd, Rn, Rm
620 SUBS-16 Rd, Rn, Rm
14634 (T?) LSL{S}.W Rd, Rn, Rm
14699 (T?) LSR{S}.W Rd, Rn, Rm
14764 (T?) ASR{S}.W Rd, Rn, Rm
14829 (T?) ROR{S}.W Rd, Rn, Rm
16661 (T1) RBIT Rd, Rm
16680 (T1) REV Rd, Rm ------------
16699 (T2) REV Rd, Rm ------------
16718 (T1) REV16 Rd, Rm ------------
[all …]
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| /external/qemu/distrib/jpeg-6b/ |
| D | testimg.ppm | 4 …Rm�Sq�St�Ru�Mm�Ut�\z�_{�\v�Uo�Ri�Re�Uf�Rb�Zh�Zh�N^�Sc�Yi�S^�`_�^W��}٩�����������������������������…
|
| /external/jpeg/ |
| D | testimg.ppm | 4 …Rm�Sq�St�Ru�Mm�Ut�\z�_{�\v�Uo�Ri�Re�Uf�Rb�Zh�Zh�N^�Sc�Yi�S^�`_�^W��}٩�����������������������������…
|
| /external/svox/pico_resources/tools/LingwareBuilding/PicoLingware_source_files/pkb/fr-FR/ |
| D | fr-FR_nk0_kpdf_mgc.pkb | 2462 �6O��2�����_)��:AWz�XFdQw~X^�g���\�|;Rm /1@9A@E\M>Ig6\`av�_q�I� "(&(93 $0FcSiD9HCMo�…
|