| /external/llvm/lib/CodeGen/ |
| D | IntrinsicLowering.cpp | 186 Value *Tmp3 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), in LowerBSWAP() local
192 Tmp3 = Builder.CreateAnd(Tmp3, in LowerBSWAP()
198 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or1"); in LowerBSWAP()
214 Value* Tmp3 = Builder.CreateLShr(V, in LowerBSWAP() local
239 Tmp3 = Builder.CreateAnd(Tmp3, in LowerBSWAP()
249 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or3"); in LowerBSWAP()
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | LegalizeDAG.cpp | 576 SDValue Tmp3 = Idx; in PerformInsertVectorEltInMemory() local
586 EVT IdxVT = Tmp3.getValueType(); in PerformInsertVectorEltInMemory()
599 Tmp3 = DAG.getNode(CastOpc, dl, PtrVT, Tmp3); in PerformInsertVectorEltInMemory()
602 Tmp3 = DAG.getNode(ISD::MUL, dl, IdxVT, Tmp3,DAG.getConstant(EltSize, IdxVT)); in PerformInsertVectorEltInMemory()
603 SDValue StackPtr2 = DAG.getNode(ISD::ADD, dl, IdxVT, Tmp3, StackPtr); in PerformInsertVectorEltInMemory()
1566 SDValue Tmp3 = Node->getOperand(2); in ExpandDYNAMIC_STACKALLOC() local
1576 unsigned Align = cast<ConstantSDNode>(Tmp3)->getZExtValue(); in ExpandDYNAMIC_STACKALLOC()
2500 SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8; in ExpandBSWAP() local
2509 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT)); in ExpandBSWAP()
2512 Tmp3 = DAG.getNode(ISD::AND, dl, VT, Tmp3, DAG.getConstant(0xFF0000, VT)); in ExpandBSWAP()
[all …]
|
| D | LegalizeFloatTypes.cpp | 1284 SDValue Tmp1, Tmp2, Tmp3; in FloatExpandSetCCOperands() local
1289 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2); in FloatExpandSetCCOperands()
1295 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3); in FloatExpandSetCCOperands()
|
| /external/llvm/lib/Transforms/Utils/ |
| D | IntegerDivision.cpp | 109 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor); in generateSignedDivisionCode() local
110 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1); in generateSignedDivisionCode()
240 Value *Tmp3 = Builder.CreateLShr(Dividend, SR_1); in generateUnsignedDivisionCode() local
308 R_1->addIncoming(Tmp3, Preheader); in generateUnsignedDivisionCode()
|
| /external/llvm/lib/Target/X86/ |
| D | X86ISelDAGToDAG.cpp | 1497 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in SelectAtomic64() local
1498 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) in SelectAtomic64()
1502 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain}; in SelectAtomic64()
1699 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in SelectAtomicLoadArith() local
1700 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) in SelectAtomicLoadArith()
1772 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain }; in SelectAtomicLoadArith()
1776 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain }; in SelectAtomicLoadArith()
2249 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; in Select() local
2250 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
2253 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4); in Select()
[all …]
|
| D | X86ISelLowering.cpp | 7920 SDValue Tmp2, Tmp3; in LowerShiftParts() local
7923 Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt); in LowerShiftParts()
7926 Tmp3 = DAG.getNode(isSRA ? ISD::SRA : ISD::SRL, dl, VT, ShOpHi, ShAmt); in LowerShiftParts()
7936 SDValue Ops0[4] = { Tmp2, Tmp3, CC, Cond }; in LowerShiftParts()
7937 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond }; in LowerShiftParts()
|
| /external/clang/lib/CodeGen/ |
| D | CGExprComplex.cpp | 554 llvm::Value *Tmp3 = Builder.CreateFAdd(Tmp1, Tmp2); // ac+bd in EmitBinDiv() local
564 DSTr = Builder.CreateFDiv(Tmp3, Tmp6); in EmitBinDiv()
570 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd in EmitBinDiv() local
581 DSTr = Builder.CreateUDiv(Tmp3, Tmp6); in EmitBinDiv()
584 DSTr = Builder.CreateSDiv(Tmp3, Tmp6); in EmitBinDiv()
|
| /external/webrtc/src/modules/audio_coding/codecs/isac/main/source/ |
| D | structs.h | 253 double Tmp3[MAXFFTSIZE]; member
|
| D | fft.c | 338 …if (fftstate->Tmp0 == NULL || fftstate->Tmp1 == NULL || fftstate->Tmp2 == NULL || fftstate->Tmp3 =… in FFTRADIX()
347 Sin = (REAL *) fftstate->Tmp3; in FFTRADIX()
|
| /external/llvm/lib/Target/NVPTX/ |
| D | NVPTXISelLowering.cpp | 974 SDValue Tmp3 = ST->getValue(); in LowerSTOREi1() local
975 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only"); in LowerSTOREi1()
979 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, in LowerSTOREi1()
980 MVT::i8, Tmp3); in LowerSTOREi1()
981 SDValue Result = DAG.getStore(Tmp1, dl, Tmp3, Tmp2, in LowerSTOREi1()
|
| /external/llvm/lib/Target/XCore/ |
| D | XCoreISelLowering.cpp | 768 SDValue Tmp3 = DAG.getNode(ISD::ADD, dl, getPointerTy(), VAList, in LowerVAARG() local
772 Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Node->getOperand(1), in LowerVAARG()
775 return DAG.getLoad(VT, dl, Tmp3, VAList, MachinePointerInfo(), in LowerVAARG()
|
| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 4856 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1); in LowerSHL_PARTS() local
4857 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3); in LowerSHL_PARTS()
4885 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRL_PARTS() local
4886 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRL_PARTS()
4913 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1); in LowerSRA_PARTS() local
4914 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3); in LowerSRA_PARTS()
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 3545 SDValue Tmp3 = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt); in LowerShiftLeftParts() local
3552 SDValue Hi = DAG.getNode(ARMISD::CMOV, dl, VT, FalseVal, Tmp3, ARMcc, in LowerShiftLeftParts()
|