| /external/llvm/lib/Target/R600/ |
| D | AMDILISelLowering.cpp | 195 setOperationAction(ISD::UDIV, MVT::v2i8, Expand); in InitAMDILLowering()
196 setOperationAction(ISD::UDIV, MVT::v4i8, Expand); in InitAMDILLowering()
197 setOperationAction(ISD::UDIV, MVT::v2i16, Expand); in InitAMDILLowering()
198 setOperationAction(ISD::UDIV, MVT::v4i16, Expand); in InitAMDILLowering()
530 r0 = DAG.getNode(ISD::UDIV, DL, OVT, r0, r1); in LowerSDIV32()
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| D | AMDGPUISelLowering.cpp | 63 setOperationAction(ISD::UDIV, MVT::i32, Expand); in AMDGPUTargetLowering()
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| D | R600ISelLowering.cpp | 49 setOperationAction(ISD::UDIV, MVT::v4i32, Expand); in R600TargetLowering()
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| /external/openssl/crypto/bn/asm/ |
| D | ppc.pl | 116 $UDIV= "divwu"; # unsigned divide
140 $UDIV= "divdu"; # unsigned divide
1670 $UDIV r8,r3,r9 #q = h/dh
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| /external/llvm/include/llvm/CodeGen/ |
| D | ISDOpcodes.h | 188 ADD, SUB, MUL, SDIV, UDIV, SREM, UREM, enumerator
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelDAGToDAG.cpp | 148 case ISD::UDIV: { in Select()
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| D | SparcInstrInfo.td | 495 defm UDIV : F3_12np<"udiv", 0b001110>;
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| /external/llvm/lib/CodeGen/ |
| D | TargetLoweringBase.cpp | 768 case ISD::UDIV: in canOpTrap()
1197 case UDiv: return ISD::UDIV; in InstructionOpcodeToISD()
1198 case SDiv: return ISD::UDIV; in InstructionOpcodeToISD()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | SelectionDAGBuilder.h | 483 void visitUDiv(const User &I) { visitBinary(I, ISD::UDIV); } in visitUDiv()
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| D | SelectionDAGDumper.cpp | 162 case ISD::UDIV: return "udiv"; in getOperationName()
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| D | FastISel.cpp | 988 return SelectBinaryOp(I, ISD::UDIV); in SelectOperator()
1163 } else if (Opcode == ISD::UDIV && isPowerOf2_64(Imm)) { in FastEmit_ri_()
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| D | LegalizeVectorOps.cpp | 197 case ISD::UDIV: in LegalizeOp()
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| D | LegalizeVectorTypes.cpp | 110 case ISD::UDIV: in ScalarizeVectorResult()
560 case ISD::UDIV: in SplitVectorResult()
1393 case ISD::UDIV: in WidenVectorResult()
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| D | LegalizeIntegerTypes.cpp | 112 case ISD::UDIV: in PromoteIntegerResult()
1127 case ISD::UDIV: ExpandIntRes_UDIV(N, Lo, Hi); break; in ExpandIntegerResult()
2295 SDValue DIV = DAG.getNode(ISD::UDIV, dl, VT, MUL, NotZero); in ExpandIntRes_XMULO()
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| D | SelectionDAG.cpp | 1756 case ISD::UDIV: { in ComputeMaskedBits()
2734 case ISD::UDIV: in FoldConstantArithmetic()
2845 case ISD::UDIV: in getNode()
3170 case ISD::UDIV: in getNode()
3198 case ISD::UDIV: in getNode()
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| D | LegalizeDAG.cpp | 2020 OtherOpcode = isDIV ? ISD::UREM : ISD::UDIV; in useDivRem()
3308 unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV; in ExpandNode()
3337 case ISD::UDIV: in ExpandNode()
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| D | DAGCombiner.cpp | 1107 case ISD::UDIV: return visitUDIV(N); in visit()
1880 return DAG.getNode(ISD::UDIV, N->getDebugLoc(), N1.getValueType(), in visitSDIV()
1952 return DAG.FoldConstantArithmetic(ISD::UDIV, VT, N0C, N1C); in visitUDIV()
2062 SDValue Div = DAG.getNode(ISD::UDIV, N->getDebugLoc(), VT, N0, N1); in visitUREM()
2302 SDValue Res = SimplifyNodeWithTwoResults(N, ISD::UDIV, ISD::UREM); in visitUDIVREM()
9292 if (N->getOpcode() == ISD::SDIV || N->getOpcode() == ISD::UDIV || in SimplifyVBinOp()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430ISelLowering.cpp | 154 setOperationAction(ISD::UDIV, MVT::i8, Expand); in MSP430TargetLowering()
160 setOperationAction(ISD::UDIV, MVT::i16, Expand); in MSP430TargetLowering()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonISelLowering.cpp | 1100 setOperationAction(ISD::UDIV, MVT::i32, Expand); in HexagonTargetLowering()
1103 setOperationAction(ISD::UDIV, MVT::i64, Expand); in HexagonTargetLowering()
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeISelLowering.cpp | 122 setOperationAction(ISD::UDIV, MVT::i32, Expand); in MBlazeTargetLowering()
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| /external/llvm/include/llvm/Target/ |
| D | TargetSelectionDAG.td | 325 def udiv : SDNode<"ISD::UDIV" , SDTIntBinOp>;
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| /external/llvm/lib/Target/Mips/ |
| D | MipsISelLowering.cpp | 272 setOperationAction(ISD::UDIV, MVT::i32, Expand); in MipsTargetLowering()
276 setOperationAction(ISD::UDIV, MVT::i64, Expand); in MipsTargetLowering()
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| D | MipsInstrInfo.td | 925 def UDIV : Div<MipsDivRemU, "divu", IIIdiv, CPURegsOpnd, [HI, LO]>,
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| /external/llvm/lib/Target/ARM/ |
| D | ARMISelLowering.cpp | 145 setOperationAction(ISD::UDIV, VT, Expand); in addTypeForNEON()
551 setOperationAction(ISD::UDIV, MVT::v4i16, Custom); in ARMTargetLowering()
552 setOperationAction(ISD::UDIV, MVT::v8i8, Custom); in ARMTargetLowering()
682 setOperationAction(ISD::UDIV, MVT::i32, Expand); in ARMTargetLowering()
5602 case ISD::UDIV: return LowerUDIV(Op, DAG); in LowerOperation()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 1696 // Contains: CRC32C?[BHWX], UDIV, SDIV, LSLV, LSRV, ASRV, RORV + aliases LSL,
1761 defm UDIV : dp_2src<0b000010, "udiv", udiv>;
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