| /external/llvm/include/llvm/MC/ |
| D | MCInstrItineraries.h | 204 unsigned UseClass, unsigned UseIdx) const { in hasPipelineForwarding() argument
214 if ((FirstUseIdx + UseIdx) >= LastUseIdx) in hasPipelineForwarding()
218 Forwardings[FirstUseIdx + UseIdx]; in hasPipelineForwarding()
225 unsigned UseClass, unsigned UseIdx) const { in getOperandLatency() argument
233 int UseCycle = getOperandCycle(UseClass, UseIdx); in getOperandLatency()
239 hasPipelineForwarding(DefClass, DefIdx, UseClass, UseIdx)) in getOperandLatency()
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| D | MCSubtargetInfo.h | 110 int getReadAdvanceCycles(const MCSchedClassDesc *SC, unsigned UseIdx, in getReadAdvanceCycles() argument
117 if (I->UseIdx < UseIdx) in getReadAdvanceCycles()
119 if (I->UseIdx > UseIdx) in getReadAdvanceCycles()
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| D | MCSchedule.h | 79 unsigned UseIdx; member
84 return UseIdx == Other.UseIdx && WriteResourceID == Other.WriteResourceID
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| /external/llvm/lib/CodeGen/ |
| D | LiveRangeEdit.cpp | 80 SlotIndex UseIdx) { in allUsesAvailableAt() argument
82 UseIdx = UseIdx.getRegSlot(true); in allUsesAvailableAt()
103 if (SlotIndex::isSameInstr(OrigIdx, UseIdx)) in allUsesAvailableAt()
106 if (OVNI != li.getVNInfoAt(UseIdx)) in allUsesAvailableAt()
113 SlotIndex UseIdx, in canRematerializeAt() argument
136 if (!allUsesAvailableAt(RM.OrigMI, DefIdx, UseIdx)) in canRematerializeAt()
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| D | TargetSchedule.cpp | 166 unsigned UseIdx = 0; in findUseIdx() local
170 ++UseIdx; in findUseIdx()
172 return UseIdx; in findUseIdx()
228 unsigned UseIdx = findUseIdx(UseMI, UseOperIdx); in computeOperandLatency() local
229 return Latency - STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID); in computeOperandLatency()
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| D | TargetInstrInfo.cpp | 576 SDNode *UseNode, unsigned UseIdx) const { in getOperandLatency()
587 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
661 const MachineInstr *UseMI, unsigned UseIdx) const { in getOperandLatency()
664 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
712 const MachineInstr *UseMI, unsigned UseIdx, in computeOperandLatency() argument
723 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx); in computeOperandLatency()
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| D | InlineSpiller.cpp | 835 SlotIndex UseIdx = LIS.getInstructionIndex(MI).getRegSlot(true); in reMaterializeFor() local
836 VNInfo *ParentVNI = VirtReg.getVNInfoAt(UseIdx.getBaseIndex()); in reMaterializeFor()
845 DEBUG(dbgs() << UseIdx << '\t' << *MI); in reMaterializeFor()
857 if (!Edit->canRematerializeAt(RM, UseIdx, false)) { in reMaterializeFor()
859 DEBUG(dbgs() << "\tcannot remat for " << UseIdx << '\t' << *MI); in reMaterializeFor()
870 DEBUG(dbgs() << "\tcannot remat tied reg: " << UseIdx << '\t' << *MI); in reMaterializeFor()
901 DEBUG(dbgs() << "\t " << UseIdx << '\t' << *MI); in reMaterializeFor()
904 NewLI.addRange(LiveRange(DefIdx, UseIdx.getRegSlot(), DefVNI)); in reMaterializeFor()
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| D | SplitKit.h | 317 SlotIndex UseIdx,
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| D | MachineVerifier.cpp | 993 SlotIndex UseIdx = LiveInts->getInstructionIndex(MI); in checkLiveness() local
998 LiveRangeQuery LRQ(*LI, UseIdx); in checkLiveness()
1001 *OS << UseIdx << " is not live in " << PrintRegUnit(*Units, TRI) in checkLiveness()
1016 LiveRangeQuery LRQ(LI, UseIdx); in checkLiveness()
1019 *OS << UseIdx << " is not live in " << LI << '\n'; in checkLiveness()
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| D | RegisterCoalescer.cpp | 630 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI); in removeCopyByCommutingDef() local
631 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); in removeCopyByCommutingDef()
682 SlotIndex UseIdx = LIS->getInstructionIndex(UseMI).getRegSlot(true); in removeCopyByCommutingDef() local
683 LiveInterval::iterator ULR = IntA.FindLiveRangeContaining(UseIdx); in removeCopyByCommutingDef()
702 SlotIndex DefIdx = UseIdx.getRegSlot(); in removeCopyByCommutingDef()
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| D | TwoAddressInstructionPass.cpp | 1454 SlotIndex UseIdx = MIIdx.getRegSlot(IsEarlyClobber); in processTiedPairs() local
1455 if (I->end == UseIdx) in processTiedPairs()
1456 LI.removeRange(LastCopyIdx, UseIdx); in processTiedPairs()
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| D | MachineInstr.cpp | 1109 void MachineInstr::tieOperands(unsigned DefIdx, unsigned UseIdx) { in tieOperands() argument
1111 MachineOperand &UseMO = getOperand(UseIdx); in tieOperands()
1128 DefMO.TiedTo = std::min(UseIdx + 1, TiedMax); in tieOperands()
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| D | SplitKit.cpp | 430 SlotIndex UseIdx, in defFromParent() argument
443 if (Edit->canRematerializeAt(RM, UseIdx, true)) { in defFromParent()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMBaseInstrInfo.h | 226 const MachineInstr *UseMI, unsigned UseIdx) const;
230 SDNode *UseNode, unsigned UseIdx) const;
258 unsigned UseIdx, unsigned UseAlign) const;
262 unsigned UseIdx, unsigned UseAlign) const;
267 unsigned UseIdx, unsigned UseAlign) const;
279 const MachineInstr *UseMI, unsigned UseIdx) const;
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| D | ARMBaseInstrInfo.cpp | 2862 unsigned UseIdx, unsigned UseAlign) const { in getVSTMUseCycle() argument
2863 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getVSTMUseCycle()
2865 return ItinData->getOperandCycle(UseClass, UseIdx); in getVSTMUseCycle()
2902 unsigned UseIdx, unsigned UseAlign) const { in getSTMUseCycle() argument
2903 int RegNo = (int)(UseIdx+1) - UseMCID.getNumOperands() + 1; in getSTMUseCycle()
2905 return ItinData->getOperandCycle(UseClass, UseIdx); in getSTMUseCycle()
2932 unsigned UseIdx, unsigned UseAlign) const { in getOperandLatency() argument
2936 if (DefIdx < DefMCID.getNumDefs() && UseIdx < UseMCID.getNumOperands()) in getOperandLatency()
2937 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx); in getOperandLatency()
2987 UseCycle = ItinData->getOperandCycle(UseClass, UseIdx); in getOperandLatency()
[all …]
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| /external/llvm/include/llvm/CodeGen/ |
| D | LiveRangeEdit.h | 86 SlotIndex UseIdx);
163 SlotIndex UseIdx,
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| D | MachineInstr.h | 832 void tieOperands(unsigned DefIdx, unsigned UseIdx);
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| /external/llvm/include/llvm/Target/ |
| D | TargetInstrInfo.h | 800 SDNode *UseNode, unsigned UseIdx) const;
813 unsigned UseIdx) const;
821 const MachineInstr *UseMI, unsigned UseIdx,
854 const MachineInstr *UseMI, unsigned UseIdx) const { in hasHighOperandLatency() argument
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| /external/llvm/utils/TableGen/ |
| D | SubtargetEmitter.cpp | 978 for (unsigned UseIdx = 0, EndIdx = Reads.size(); in GenSchedClassTables() local
979 UseIdx != EndIdx; ++UseIdx) { in GenSchedClassTables()
981 FindReadAdvance(SchedModels.getSchedRead(Reads[UseIdx]), ProcModel); in GenSchedClassTables()
1003 RAEntry.UseIdx = UseIdx; in GenSchedClassTables()
1115 OS << " {" << RAEntry.UseIdx << ", " in EmitSchedClassTables()
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| /external/llvm/lib/Target/X86/ |
| D | X86InstrInfo.h | 376 const MachineInstr *UseMI, unsigned UseIdx) const;
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| D | X86InstrInfo.cpp | 4704 const MachineInstr *UseMI, unsigned UseIdx) const { in hasHighOperandLatency()
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | InstrEmitter.cpp | 950 unsigned UseIdx = GroupIdx.back() + 1; in EmitSpecialNode() local
952 MIB->tieOperands(DefIdx + j, UseIdx + j); in EmitSpecialNode()
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