| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 263 MBB.addLiveIn(SuperReg); in spillCalleeSavedRegisters()
271 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
317 MBB.addLiveIn(SuperReg); in restoreCalleeSavedRegisters()
324 MBB.addLiveIn(Reg); in restoreCalleeSavedRegisters()
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| D | HexagonCFGOptimizer.cpp | 217 LayoutSucc->addLiveIn(NewLiveIn[i]); in runOnMachineFunction()
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| /external/llvm/lib/Target/Mips/ |
| D | MipsSEISelDAGToDAG.cpp | 100 MF.getRegInfo().addLiveIn(Mips::T9_64); in initGlobalBaseReg()
101 MBB.addLiveIn(Mips::T9_64); in initGlobalBaseReg()
128 MF.getRegInfo().addLiveIn(Mips::T9); in initGlobalBaseReg()
129 MBB.addLiveIn(Mips::T9); in initGlobalBaseReg()
163 MF.getRegInfo().addLiveIn(Mips::V0); in initGlobalBaseReg()
164 MBB.addLiveIn(Mips::V0); in initGlobalBaseReg()
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| D | MipsSEFrameLowering.cpp | 127 MBB.addLiveIn(ehDataReg(I)); in emitPrologue()
231 EntryBlock->addLiveIn(Reg); in spillCalleeSavedRegisters()
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| D | Mips16FrameLowering.cpp | 122 EntryBlock->addLiveIn(Reg); in spillCalleeSavedRegisters()
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| /external/llvm/lib/Target/XCore/ |
| D | XCoreFrameLowering.cpp | 126 MBB.addLiveIn(XCore::LR); in emitPrologue()
154 MBB.addLiveIn(XCore::LR); in emitPrologue()
171 MBB.addLiveIn(XCore::R10); in emitPrologue()
289 MBB.addLiveIn(it->getReg()); in spillCalleeSavedRegisters()
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| /external/llvm/lib/Target/MSP430/ |
| D | MSP430FrameLowering.cpp | 76 I->addLiveIn(MSP430::FPW); in emitPrologue()
198 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
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| /external/llvm/lib/CodeGen/ |
| D | MachineRegisterInfo.cpp | 329 EntryMBB->addLiveIn(LiveIns[i].first); in EmitLiveInCopies()
333 EntryMBB->addLiveIn(LiveIns[i].first); in EmitLiveInCopies()
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| D | VirtRegMap.cpp | 257 LiveIn[i]->addLiveIn(PhysReg); in addMBBLiveIns()
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| D | PrologEpilogInserter.cpp | 300 EntryBlock->addLiveIn(CSI[i].getReg()); in insertCSRSpillsAndRestores()
375 MBB->addLiveIn(blockCSI[i].getReg()); in insertCSRSpillsAndRestores()
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| D | MachineFunction.cpp | 417 unsigned MachineFunction::addLiveIn(unsigned PReg, in addLiveIn() function in MachineFunction
426 MRI.addLiveIn(PReg, VReg); in addLiveIn()
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| D | BranchFolding.cpp | 387 NewMBB->addLiveIn(i); in MaintainLiveIns()
1718 TBB->addLiveIn(Def); in HoistCommonCodeInSuccs()
1719 FBB->addLiveIn(Def); in HoistCommonCodeInSuccs()
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| /external/llvm/lib/Target/X86/ |
| D | X86FrameLowering.cpp | 807 I->addLiveIn(FramePtr); in emitPrologue()
1265 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
1285 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
1460 allocMBB->addLiveIn(*i); in adjustForSegmentedStacks()
1461 checkMBB->addLiveIn(*i); in adjustForSegmentedStacks()
1465 allocMBB->addLiveIn(X86::R10); in adjustForSegmentedStacks()
1702 stackCheckMBB->addLiveIn(*I); in adjustForHiPEPrologue()
1703 incStackMBB->addLiveIn(*I); in adjustForHiPEPrologue()
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| /external/dexmaker/src/dx/java/com/android/dx/ssa/back/ |
| D | LivenessAnalyzer.java | 219 blockN.addLiveIn(regV); in liveInAtStatement()
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| /external/llvm/lib/Target/R600/ |
| D | SIISelLowering.cpp | 169 Reg = MF.addLiveIn(Reg, &AMDGPU::SReg_64RegClass); in LowerFormalArguments()
176 Reg = MF.addLiveIn(Reg, RC); in LowerFormalArguments()
190 Reg = MF.addLiveIn(Reg, RC); in LowerFormalArguments()
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| D | AMDGPUIndirectAddressing.cpp | 135 (*Succ)->addLiveIn(Key->second); in runOnMachineFunction()
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| D | AMDGPUISelLowering.cpp | 378 MRI.addLiveIn(Reg, VirtualRegister); in CreateLiveInRegister()
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| /external/llvm/lib/Target/ARM/ |
| D | ARMFrameLowering.cpp | 614 MBB.addLiveIn(Reg); in emitPushInst()
806 MBB.addLiveIn(SupReg); in emitAlignedDPRCS2Spills()
824 MBB.addLiveIn(SupReg); in emitAlignedDPRCS2Spills()
836 MBB.addLiveIn(SupReg); in emitAlignedDPRCS2Spills()
845 MBB.addLiveIn(NextReg); in emitAlignedDPRCS2Spills()
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| D | Thumb1FrameLowering.cpp | 359 MBB.addLiveIn(Reg); in spillCalleeSavedRegisters()
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| /external/llvm/include/llvm/CodeGen/ |
| D | MachineRegisterInfo.h | 472 void addLiveIn(unsigned Reg, unsigned vreg = 0) {
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| D | MachineFunction.h | 310 unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
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| D | MachineBasicBlock.h | 294 void addLiveIn(unsigned Reg) { LiveIns.push_back(Reg); }
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| /external/llvm/lib/Target/PowerPC/ |
| D | PPCISelLowering.cpp | 1953 unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC); in LowerFormalArguments_32SVR4()
2045 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass); in LowerFormalArguments_32SVR4()
2064 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass); in LowerFormalArguments_32SVR4()
2233 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
2272 VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
2295 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
2322 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass); in LowerFormalArguments_64SVR4()
2324 VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass); in LowerFormalArguments_64SVR4()
2342 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); in LowerFormalArguments_64SVR4()
2397 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); in LowerFormalArguments_64SVR4()
[all …]
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| /external/llvm/lib/Target/MBlaze/ |
| D | MBlazeInstrInfo.cpp | 293 RegInfo.addLiveIn(MBlaze::R20); in getGlobalBaseReg()
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| /external/llvm/lib/Target/Sparc/ |
| D | SparcISelLowering.cpp | 183 MF.getRegInfo().addLiveIn(VA.getLocReg(), VRegHi); in LowerFormalArguments()
198 unsigned loReg = MF.addLiveIn(NextVA.getLocReg(), in LowerFormalArguments()
209 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg); in LowerFormalArguments()
321 MF.getRegInfo().addLiveIn(*CurArgReg, VReg); in LowerFormalArguments()
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